The Experts below are selected from a list of 327 Experts worldwide ranked by ideXlab platform

Majid Sarrafzadeh - One of the best experts on this subject based on the ideXlab platform.

  • Potential slack: an effective metric of Combinational Circuit performance
    IEEE ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE ACM Digest of Technical Papers (Cat. No.00CH37140), 2000
    Co-Authors: Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh
    Abstract:

    This paper proposes the concept of potential slack and shows that it is an effective metric of Combinational Circuit performance. We provide several methods for estimating potential slack and prove one (a maximal-independent-set based algorithm) in particular which works best. Experiments in gate sizing show that potential slack provides 100% correct prediction for Circuit area optimization. We also explore the role of potential slack in timing-driven placement.

  • ICCAD - Potential slack: an effective metric of Combinational Circuit performance
    IEEE ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE ACM Digest of Technical Papers (Cat. No.00CH37140), 1
    Co-Authors: Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh
    Abstract:

    This paper proposes the concept of potential slack and show it is an effective metric of Combinational Circuit performance. We provide several methods for estimating potential slack and prove one (a maximal-independent-set based algorithm) in particular works best. Experiments in gate sizing show that potential slack provides 100% correct prediction for Circuit area optimization. We also explore the role of potential slack in timing-driven placement.

Chunhong Chen - One of the best experts on this subject based on the ideXlab platform.

  • Potential slack: an effective metric of Combinational Circuit performance
    IEEE ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE ACM Digest of Technical Papers (Cat. No.00CH37140), 2000
    Co-Authors: Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh
    Abstract:

    This paper proposes the concept of potential slack and shows that it is an effective metric of Combinational Circuit performance. We provide several methods for estimating potential slack and prove one (a maximal-independent-set based algorithm) in particular which works best. Experiments in gate sizing show that potential slack provides 100% correct prediction for Circuit area optimization. We also explore the role of potential slack in timing-driven placement.

  • ICCAD - Potential slack: an effective metric of Combinational Circuit performance
    IEEE ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE ACM Digest of Technical Papers (Cat. No.00CH37140), 1
    Co-Authors: Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh
    Abstract:

    This paper proposes the concept of potential slack and show it is an effective metric of Combinational Circuit performance. We provide several methods for estimating potential slack and prove one (a maximal-independent-set based algorithm) in particular works best. Experiments in gate sizing show that potential slack provides 100% correct prediction for Circuit area optimization. We also explore the role of potential slack in timing-driven placement.

Xiaojian Yang - One of the best experts on this subject based on the ideXlab platform.

  • Potential slack: an effective metric of Combinational Circuit performance
    IEEE ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE ACM Digest of Technical Papers (Cat. No.00CH37140), 2000
    Co-Authors: Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh
    Abstract:

    This paper proposes the concept of potential slack and shows that it is an effective metric of Combinational Circuit performance. We provide several methods for estimating potential slack and prove one (a maximal-independent-set based algorithm) in particular which works best. Experiments in gate sizing show that potential slack provides 100% correct prediction for Circuit area optimization. We also explore the role of potential slack in timing-driven placement.

  • ICCAD - Potential slack: an effective metric of Combinational Circuit performance
    IEEE ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE ACM Digest of Technical Papers (Cat. No.00CH37140), 1
    Co-Authors: Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh
    Abstract:

    This paper proposes the concept of potential slack and show it is an effective metric of Combinational Circuit performance. We provide several methods for estimating potential slack and prove one (a maximal-independent-set based algorithm) in particular works best. Experiments in gate sizing show that potential slack provides 100% correct prediction for Circuit area optimization. We also explore the role of potential slack in timing-driven placement.

Brenda Luderman - One of the best experts on this subject based on the ideXlab platform.

  • A Logic Programming Framework for Combinational Circuit Synthesis
    arXiv: Logic in Computer Science, 2008
    Co-Authors: Paul Tarau, Brenda Luderman
    Abstract:

    Logic Programming languages and Combinational Circuit synthesis tools share a common "combinatorial search over logic formulae" background. This paper attempts to reconnect the two fields with a fresh look at Prolog encodings for the combinatorial objects involved in Circuit synthesis. While benefiting from Prolog's fast unification algorithm and built-in backtracking mechanism, efficiency of our search algorithm is ensured by using parallel bitstring operations together with logic variable equality propagation, as a mapping mechanism from primary inputs to the leaves of candidate Leaf-DAGs implementing a Combinational Circuit specification. After an exhaustive expressiveness comparison of various minimal libraries, a surprising first-runner, Strict Boolean Inequality "

  • a logic programming framework for Combinational Circuit synthesis
    arXiv: Logic in Computer Science, 2008
    Co-Authors: Paul Tarau, Brenda Luderman
    Abstract:

    Logic Programming languages and Combinational Circuit synthesis tools share a common "combinatorial search over logic formulae" background. This paper attempts to reconnect the two fields with a fresh look at Prolog encodings for the combinatorial objects involved in Circuit synthesis. While benefiting from Prolog's fast unification algorithm and built-in backtracking mechanism, efficiency of our search algorithm is ensured by using parallel bitstring operations together with logic variable equality propagation, as a mapping mechanism from primary inputs to the leaves of candidate Leaf-DAGs implementing a Combinational Circuit specification. After an exhaustive expressiveness comparison of various minimal libraries, a surprising first-runner, Strict Boolean Inequality "<" together with constant function "1" also turns out to have small transistor-count implementations, competitive to NAND-only or NOR-only libraries. As a practical outcome, a more realistic Circuit synthesizer is implemented that combines rewriting-based simplification of (<,1) Circuits with exhaustive Leaf-DAG Circuit search. Keywords: logic programming and Circuit design, combinatorial object generation, exact Combinational Circuit synthesis, universal boolean logic libraries, symbolic rewriting, minimal transistor-count Circuit synthesis

  • revisiting exact Combinational Circuit synthesis
    ACM Symposium on Applied Computing, 2008
    Co-Authors: Paul Tarau, Brenda Luderman
    Abstract:

    The paper revisits exact Combinational Circuit synthesis with logic programming tools. Our focus is finding a minimal cost Circuit that matches a specification - a notoriously hard nondeterministic search problem. After an exhaustive expressiveness comparison of various minimal libraries, two asymmetrical operations, Logical Implication "⇒" and Strict Boolean Inequality "<" turn out to consistently outperform their more popular symmetrical couterparts NAND and NOR, while having comparably small transistor count implementations. The code of the synthetizer and various libraries is available at http://logic.csci.unt.edu/tarau/research/2007/Isyn.zip.

  • SAC - Revisiting exact Combinational Circuit synthesis
    Proceedings of the 2008 ACM symposium on Applied computing - SAC '08, 2008
    Co-Authors: Paul Tarau, Brenda Luderman
    Abstract:

    The paper revisits exact Combinational Circuit synthesis with logic programming tools. Our focus is finding a minimal cost Circuit that matches a specification - a notoriously hard nondeterministic search problem. After an exhaustive expressiveness comparison of various minimal libraries, two asymmetrical operations, Logical Implication "⇒" and Strict Boolean Inequality "

  • a logic programming framework for Combinational Circuit synthesis
    International Conference on Logic Programming, 2007
    Co-Authors: Paul Tarau, Brenda Luderman
    Abstract:

    Logic Programming languages and Combinational Circuit synthesis tools share a common "combinatorial search over logic formulae" background. This paper attempts to reconnect the two fields with a fresh look at Prolog encodings for the combinatorial objects involved in Circuit synthesis. While benefiting from Prolog's fast unification algorithm and built-in backtracking mechanism, efficiency of our search algorithm is ensured by using parallel bitstring operations together with logic variable equality propagation, as a mapping mechanism from primary inputs to the leaves of candidate Leaf-DAGs implementing a Combinational Circuit specification. After an exhaustive expressiveness comparison of various minimal libraries, a surprising first-runner, Strict Boolean Inequality "<" together with constant function "1" also turns out to have small transistor-count implementations, competitive to NAND-only or NOR-only libraries. As a practical outcome, a more realistic Circuit synthesizer is implemented that combines rewriting-based simplification of (<, 1) Circuits with exhaustive Leaf-DAG Circuit search.

A. Matrosova - One of the best experts on this subject based on the ideXlab platform.

  • masking internal node faults and trojan Circuits in logical Circuits
    East-West Design and Test Symposium, 2019
    Co-Authors: A. Matrosova, V. Provkin, E. Nikolaeva
    Abstract:

    A Combinational Circuit C is considered. Masking of internal node logical faults with using the subCircuit that outputs are connected with Circuit C internal nodes that are fed by fault nodes is suggested. The sub-Circuit inputs are connected with either Circuit C inputs or with internal nodes of Circuit C that precede the fault nodes. Masking is based on applying of incompletely specified Boolean functions of internal nodes. Algorithms of deriving incompletely specified Boolean function for some internal node v are described. One of them gets the incompletely specified function that depends on input variables of Circuit C, another gets the incompletely specified Boolean function that depends on internal variables of Circuit C that corresponds to internal nodes preceding fault nodes. Using these algorithms for several fault nodes we obtain the system of incompletely specified Boolean functions that is implemented by masking (patch) Circuit. This approach may be also applied for masking Trojan Circuits (TCs). It is supposed that TC output is injected into a line of Combinational Circuit C. Experimental results are given. They demonstrate possibilities of essential cutting overhead when using patch function in comparison with duplication.

  • EWDTS - Masking Internal Node Faults and Trojan Circuits in Logical Circuits
    2019 IEEE East-West Design & Test Symposium (EWDTS), 2019
    Co-Authors: A. Matrosova, V. Provkin, E. Nikolaeva
    Abstract:

    A Combinational Circuit C is considered. Masking of internal node logical faults with using the subCircuit that outputs are connected with Circuit C internal nodes that are fed by fault nodes is suggested. The sub-Circuit inputs are connected with either Circuit C inputs or with internal nodes of Circuit C that precede the fault nodes. Masking is based on applying of incompletely specified Boolean functions of internal nodes. Algorithms of deriving incompletely specified Boolean function for some internal node v are described. One of them gets the incompletely specified function that depends on input variables of Circuit C, another gets the incompletely specified Boolean function that depends on internal variables of Circuit C that corresponds to internal nodes preceding fault nodes. Using these algorithms for several fault nodes we obtain the system of incompletely specified Boolean functions that is implemented by masking (patch) Circuit. This approach may be also applied for masking Trojan Circuits (TCs). It is supposed that TC output is injected into a line of Combinational Circuit C. Experimental results are given. They demonstrate possibilities of essential cutting overhead when using patch function in comparison with duplication.

  • forming patch functions and Combinational Circuit rectification
    East-West Design and Test Symposium, 2018
    Co-Authors: A. Matrosova, Semen Chernyshov, G Goshin, D. Kudin
    Abstract:

    Increasing chips complexity originates a problem of providing their 100% correct fabrication. During chip fabrication logical bugs may be detected, changes of specification may appear and so on. There are some ways of recovering chips to provide functioning we need. One of them is connected with using Engineering Change Order (ECO) technique. In the frame of this technique forming of patch functions is based on using internal nodes of implemented Circuit C i (Circuit that has to be corrected). Methods are oriented to cut calculations of patch functions with using SAT and QBS solvers and cut overhead. Functions of implemented Circuit C i and specification Circuit C s , as a rule, are essentially different. Our approach is oriented to slight difference between specification Circuit C s and implemented Circuit C i . We suggest using special miter system represented by list of products with their special characteristics. Our approach does not demand using SAT and QBS solvers. For correction we use only inputs and outputs of implemented Circuit C i . In contrast with current approaches there is no need using internal nodes of the implemented Circuit.

  • testing multiple stuck at faults of robdd based Combinational Circuit design
    2017 18th IEEE Latin American Test Symposium (LATS), 2017
    Co-Authors: Toral Shah, A. Matrosova, Masahiro Fujita, Binod Kumar, Virendra Singh
    Abstract:

    As technology scales, small and dense geometries, and process variations introduce defects that are often not detected by single stuck-at tests. To improve defect coverage, we expand the single stuck-at tests to cover multiple stuck-at faults. This paper investigates multiple stuck-at fault (MSAF) testability of ROBDD (Reduced Ordered Binary Decision Diagram) based fully delay testable Combinational Circuits. The Circuits are derived by covering ROBDD nodes with Invert-And-Or sub-Circuits(2:1 muxes). We show that for each sub-Circuit which acts as a partition, the multiple stuck-at fault test set needs only four vectors. Additionally we prove that multiple stuck-at fault test set for the complete Circuit has an upper bound of 3N test vectors where N is node count of the ROBDD representing the Circuit.

  • robdd based path delay fault testable Combinational Circuit synthesis
    East-West Design and Test Symposium, 2016
    Co-Authors: Toral Shah, Virendra Singh, A. Matrosova
    Abstract:

    Traditional scan based transition delay fault tests can potentially miss variability induced delay faults on long interconnects. On the other hand, an ATPG may not be successful in deriving test patterns for all paths. The paper proposes a BDD based synthesis method where all the paths are testable under the path delay fault model without addition of extra inputs. Each ROBDD (Reduced-Ordered-Binary Decision Diagram) node is covered by an Invert-AND-OR sub-Circuit. The paper proves that the synthesized Circuit is fully testable for path delay faults, either by robust tests or validatable non-robust tests.