The Experts below are selected from a list of 7428 Experts worldwide ranked by ideXlab platform

N N Mahatme - One of the best experts on this subject based on the ideXlab platform.

  • impact of technology scaling on the Combinational Logic soft error rate
    International Reliability Physics Symposium, 2014
    Co-Authors: N N Mahatme, B L Bhuva, N J Gaspard, S Jagannathan, T D Loveless, L W Massengill, S J Wen, I. Chatterjee, T R Assis, R Wong
    Abstract:

    Experimental results from alpha particle irradiation of 40-nm, 28-nm and 20-nm bulk technology circuits operating in the GHz range suggest that the Combinational Logic soft error rate (SER) per Logic gate decreases with scaling. This rate of decrease for the Logic SER with scaling, however, is not as high as that of the latch SER. As a result, the proportion of Combinational Logic soft errors at the chip level is shown to increase. Results suggest that alpha-particle Logic SER of average sized circuits is about 20% of the latch SER at 20-nm node while it is only 10% at 40-nm at 500 MHz. Moreover, the frequency at which Combinational Logic SER exceeds latch SER decreases with scaling. Factors that influence Logic soft error scaling trends, such as sensitive area, transient pulse-widths and latch characteristics, are estimated through simulations and soft-error rate predictions for future technology nodes are made.

  • Kernel-Based Circuit Partition Approach to Mitigate Combinational Logic Soft Errors
    IEEE Transactions on Nuclear Science, 2014
    Co-Authors: N N Mahatme, B L Bhuva, N J Gaspard, T D Loveless, L W Massengill, S J Wen, T. Assis, I. Chatterjee, W. H. Robinson, R Wong
    Abstract:

    With the emphasis on low-power design, achieving soft error reliability in Combinational Logic circuits is extremely challenging. In this work, a circuit partitioning technique is used to minimize dynamic power consumption and to mitigate Combinational Logic soft errors. This work shows that for certain circuits, reduction in both power and Combinational Logic soft errors is simultaneously achievable. This is accomplished by partitioning the circuit so that the effective soft error cross section decreases and idle sub-circuits can be disabled to save power. The proposed method was evaluated experimentally using a 4-bit comparator fabricated at the 20-nm bulk CMOS technology node. With the application of the proposed technique, the alpha particle Logic error cross section decreases by 30% compared to a baseline conventional circuit design. Dynamic power reduction of up to 50% is also seen for example circuits.

  • impact of supply voltage and frequency on the soft error rate of Logic circuits
    IEEE Transactions on Nuclear Science, 2013
    Co-Authors: N N Mahatme, B L Bhuva, N J Gaspard, S Jagannathan, T D Loveless, William H Robinson, L W Massengill, S J Wen, R Wong
    Abstract:

    Alpha particle irradiations of 28-nm Combinational Logic and flip-flop circuits under different supply voltage and frequency operating conditions are investigated. Results indicate that while the supply voltage has a strong impact on the alpha particle soft error rate of flip-flops, the Combinational Logic error rate is relatively unaffected by supply voltage variation. Simulations are used to explain the results and highlight the differences between low-LET alpha particle irradiation and heavy-ion irradiation as far as voltage dependence of the Logic soft error rate is concerned. Moreover, frequency has a much stronger impact on the Logic soft error rate as compared to the flip-flop soft error rate. As a result, the frequency at which soft errors from Combinational Logic circuits will exceed errors from flip-flops decreases as the voltage increases. The impact of these observations is discussed in the context of soft-error mitigation strategies.

  • reliability aware synthesis of Combinational Logic with minimal performance penalty
    IEEE Transactions on Nuclear Science, 2013
    Co-Authors: Daniel B Limbrick, N N Mahatme, William H Robinson, B L Bhuva
    Abstract:

    Strategies to mitigate soft errors in Combinational Logic have resulted in large performance penalties and increases in design time. This study alleviates these issues by using standard cells to selectively harden vulnerable nodes in Combinational Logic. Results indicate that replacing two-input gates with four-input equivalents reduces pulse widths by 5%-20% with less than 1% power overhead. Additionally, this paper demonstrates reliability gains that can be made at the synthesis level under tight performance constraints.

  • Experimental Estimation of the Window of Vulnerability for Logic Circuits
    IEEE Transactions on Nuclear Science, 2013
    Co-Authors: N N Mahatme, B L Bhuva, N J Gaspard, S Jagannathan, T D Loveless, I. Chatterjee, Lloyd W. Massengill, Ronald D. Schrimpf
    Abstract:

    Accurate estimation of single event upset rates for complex Combinational Logic circuits is extremely challenging due to the difficulties involved in calculation of different masking factors. This paper introduces the concept of an effective value of the window of vulnerability which is calculated experimentally for 28 nm bulk CMOS Combinational Logic circuits. Results suggest that the window of vulnerability for different input conditions of the same circuit are similar but that of different circuits could differ. The difference in gate type and topology is identified as the key reason for the differences in window of vulnerability. The window of vulnerability due to alpha particle irradiation for different circuits is between 30-60 ps which compares reasonably with SET pulse-width distributions reported in the past. The effective value of the window of vulnerability could be used to simplify Logic error rate calculations.

B L Bhuva - One of the best experts on this subject based on the ideXlab platform.

  • an empirical model for predicting se cross section for Combinational Logic circuits in advanced technologies
    IEEE Transactions on Nuclear Science, 2018
    Co-Authors: H Jiang, L W Massengill, Hangfang Zhang, J S Kauppila, B L Bhuva
    Abstract:

    At the gigahertz range of frequencies, contribution of Combinational Logic upsets has increased significantly to the overall single-event (SE) upset rate (SER) of sequential circuits. Most approaches for modeling and/or predicting Logic SER are either pure simulation based or pure experiment based. Simulation-based approaches need a lot of computing power. Experiment-based approaches require fabrication of actual circuits. This paper presents an empirical method that uses experimental data from simple test structures for estimating SE vulnerability of any Combinational Logic circuit. Estimated Logic SEU cross section matches well with the measured Logic SEU cross section. Estimated Logic SEU cross section results obtained with the proposed method are within $2\times $ average error when compared to the experimentally measured Logic SEU cross section. This method only needs to be calibrated once for use at a given technology node.

  • impact of technology scaling on the Combinational Logic soft error rate
    International Reliability Physics Symposium, 2014
    Co-Authors: N N Mahatme, B L Bhuva, N J Gaspard, S Jagannathan, T D Loveless, L W Massengill, S J Wen, I. Chatterjee, T R Assis, R Wong
    Abstract:

    Experimental results from alpha particle irradiation of 40-nm, 28-nm and 20-nm bulk technology circuits operating in the GHz range suggest that the Combinational Logic soft error rate (SER) per Logic gate decreases with scaling. This rate of decrease for the Logic SER with scaling, however, is not as high as that of the latch SER. As a result, the proportion of Combinational Logic soft errors at the chip level is shown to increase. Results suggest that alpha-particle Logic SER of average sized circuits is about 20% of the latch SER at 20-nm node while it is only 10% at 40-nm at 500 MHz. Moreover, the frequency at which Combinational Logic SER exceeds latch SER decreases with scaling. Factors that influence Logic soft error scaling trends, such as sensitive area, transient pulse-widths and latch characteristics, are estimated through simulations and soft-error rate predictions for future technology nodes are made.

  • Kernel-Based Circuit Partition Approach to Mitigate Combinational Logic Soft Errors
    IEEE Transactions on Nuclear Science, 2014
    Co-Authors: N N Mahatme, B L Bhuva, N J Gaspard, T D Loveless, L W Massengill, S J Wen, T. Assis, I. Chatterjee, W. H. Robinson, R Wong
    Abstract:

    With the emphasis on low-power design, achieving soft error reliability in Combinational Logic circuits is extremely challenging. In this work, a circuit partitioning technique is used to minimize dynamic power consumption and to mitigate Combinational Logic soft errors. This work shows that for certain circuits, reduction in both power and Combinational Logic soft errors is simultaneously achievable. This is accomplished by partitioning the circuit so that the effective soft error cross section decreases and idle sub-circuits can be disabled to save power. The proposed method was evaluated experimentally using a 4-bit comparator fabricated at the 20-nm bulk CMOS technology node. With the application of the proposed technique, the alpha particle Logic error cross section decreases by 30% compared to a baseline conventional circuit design. Dynamic power reduction of up to 50% is also seen for example circuits.

  • impact of supply voltage and frequency on the soft error rate of Logic circuits
    IEEE Transactions on Nuclear Science, 2013
    Co-Authors: N N Mahatme, B L Bhuva, N J Gaspard, S Jagannathan, T D Loveless, William H Robinson, L W Massengill, S J Wen, R Wong
    Abstract:

    Alpha particle irradiations of 28-nm Combinational Logic and flip-flop circuits under different supply voltage and frequency operating conditions are investigated. Results indicate that while the supply voltage has a strong impact on the alpha particle soft error rate of flip-flops, the Combinational Logic error rate is relatively unaffected by supply voltage variation. Simulations are used to explain the results and highlight the differences between low-LET alpha particle irradiation and heavy-ion irradiation as far as voltage dependence of the Logic soft error rate is concerned. Moreover, frequency has a much stronger impact on the Logic soft error rate as compared to the flip-flop soft error rate. As a result, the frequency at which soft errors from Combinational Logic circuits will exceed errors from flip-flops decreases as the voltage increases. The impact of these observations is discussed in the context of soft-error mitigation strategies.

  • reliability aware synthesis of Combinational Logic with minimal performance penalty
    IEEE Transactions on Nuclear Science, 2013
    Co-Authors: Daniel B Limbrick, N N Mahatme, William H Robinson, B L Bhuva
    Abstract:

    Strategies to mitigate soft errors in Combinational Logic have resulted in large performance penalties and increases in design time. This study alleviates these issues by using standard cells to selectively harden vulnerable nodes in Combinational Logic. Results indicate that replacing two-input gates with four-input equivalents reduces pulse widths by 5%-20% with less than 1% power overhead. Additionally, this paper demonstrates reliability gains that can be made at the synthesis level under tight performance constraints.

L W Massengill - One of the best experts on this subject based on the ideXlab platform.

  • an empirical model for predicting se cross section for Combinational Logic circuits in advanced technologies
    IEEE Transactions on Nuclear Science, 2018
    Co-Authors: H Jiang, L W Massengill, Hangfang Zhang, J S Kauppila, B L Bhuva
    Abstract:

    At the gigahertz range of frequencies, contribution of Combinational Logic upsets has increased significantly to the overall single-event (SE) upset rate (SER) of sequential circuits. Most approaches for modeling and/or predicting Logic SER are either pure simulation based or pure experiment based. Simulation-based approaches need a lot of computing power. Experiment-based approaches require fabrication of actual circuits. This paper presents an empirical method that uses experimental data from simple test structures for estimating SE vulnerability of any Combinational Logic circuit. Estimated Logic SEU cross section matches well with the measured Logic SEU cross section. Estimated Logic SEU cross section results obtained with the proposed method are within $2\times $ average error when compared to the experimentally measured Logic SEU cross section. This method only needs to be calibrated once for use at a given technology node.

  • impact of technology scaling on the Combinational Logic soft error rate
    International Reliability Physics Symposium, 2014
    Co-Authors: N N Mahatme, B L Bhuva, N J Gaspard, S Jagannathan, T D Loveless, L W Massengill, S J Wen, I. Chatterjee, T R Assis, R Wong
    Abstract:

    Experimental results from alpha particle irradiation of 40-nm, 28-nm and 20-nm bulk technology circuits operating in the GHz range suggest that the Combinational Logic soft error rate (SER) per Logic gate decreases with scaling. This rate of decrease for the Logic SER with scaling, however, is not as high as that of the latch SER. As a result, the proportion of Combinational Logic soft errors at the chip level is shown to increase. Results suggest that alpha-particle Logic SER of average sized circuits is about 20% of the latch SER at 20-nm node while it is only 10% at 40-nm at 500 MHz. Moreover, the frequency at which Combinational Logic SER exceeds latch SER decreases with scaling. Factors that influence Logic soft error scaling trends, such as sensitive area, transient pulse-widths and latch characteristics, are estimated through simulations and soft-error rate predictions for future technology nodes are made.

  • Kernel-Based Circuit Partition Approach to Mitigate Combinational Logic Soft Errors
    IEEE Transactions on Nuclear Science, 2014
    Co-Authors: N N Mahatme, B L Bhuva, N J Gaspard, T D Loveless, L W Massengill, S J Wen, T. Assis, I. Chatterjee, W. H. Robinson, R Wong
    Abstract:

    With the emphasis on low-power design, achieving soft error reliability in Combinational Logic circuits is extremely challenging. In this work, a circuit partitioning technique is used to minimize dynamic power consumption and to mitigate Combinational Logic soft errors. This work shows that for certain circuits, reduction in both power and Combinational Logic soft errors is simultaneously achievable. This is accomplished by partitioning the circuit so that the effective soft error cross section decreases and idle sub-circuits can be disabled to save power. The proposed method was evaluated experimentally using a 4-bit comparator fabricated at the 20-nm bulk CMOS technology node. With the application of the proposed technique, the alpha particle Logic error cross section decreases by 30% compared to a baseline conventional circuit design. Dynamic power reduction of up to 50% is also seen for example circuits.

  • impact of supply voltage and frequency on the soft error rate of Logic circuits
    IEEE Transactions on Nuclear Science, 2013
    Co-Authors: N N Mahatme, B L Bhuva, N J Gaspard, S Jagannathan, T D Loveless, William H Robinson, L W Massengill, S J Wen, R Wong
    Abstract:

    Alpha particle irradiations of 28-nm Combinational Logic and flip-flop circuits under different supply voltage and frequency operating conditions are investigated. Results indicate that while the supply voltage has a strong impact on the alpha particle soft error rate of flip-flops, the Combinational Logic error rate is relatively unaffected by supply voltage variation. Simulations are used to explain the results and highlight the differences between low-LET alpha particle irradiation and heavy-ion irradiation as far as voltage dependence of the Logic soft error rate is concerned. Moreover, frequency has a much stronger impact on the Logic soft error rate as compared to the flip-flop soft error rate. As a result, the frequency at which soft errors from Combinational Logic circuits will exceed errors from flip-flops decreases as the voltage increases. The impact of these observations is discussed in the context of soft-error mitigation strategies.

  • layout technique for single event transient mitigation via pulse quenching
    IEEE Transactions on Nuclear Science, 2011
    Co-Authors: N M Atkinson, B L Bhuva, J R Ahlbin, A F Witulski, W T Holman, L W Massengill
    Abstract:

    A layout technique that exploits single-event transient pulse quenching to mitigate transients in Combinational Logic is presented. TCAD simulations show as much as 60% reduction in sensitive area and 70% reduction in pulse width for some Logic cells.

R Wong - One of the best experts on this subject based on the ideXlab platform.

  • impact of technology scaling on the Combinational Logic soft error rate
    International Reliability Physics Symposium, 2014
    Co-Authors: N N Mahatme, B L Bhuva, N J Gaspard, S Jagannathan, T D Loveless, L W Massengill, S J Wen, I. Chatterjee, T R Assis, R Wong
    Abstract:

    Experimental results from alpha particle irradiation of 40-nm, 28-nm and 20-nm bulk technology circuits operating in the GHz range suggest that the Combinational Logic soft error rate (SER) per Logic gate decreases with scaling. This rate of decrease for the Logic SER with scaling, however, is not as high as that of the latch SER. As a result, the proportion of Combinational Logic soft errors at the chip level is shown to increase. Results suggest that alpha-particle Logic SER of average sized circuits is about 20% of the latch SER at 20-nm node while it is only 10% at 40-nm at 500 MHz. Moreover, the frequency at which Combinational Logic SER exceeds latch SER decreases with scaling. Factors that influence Logic soft error scaling trends, such as sensitive area, transient pulse-widths and latch characteristics, are estimated through simulations and soft-error rate predictions for future technology nodes are made.

  • Kernel-Based Circuit Partition Approach to Mitigate Combinational Logic Soft Errors
    IEEE Transactions on Nuclear Science, 2014
    Co-Authors: N N Mahatme, B L Bhuva, N J Gaspard, T D Loveless, L W Massengill, S J Wen, T. Assis, I. Chatterjee, W. H. Robinson, R Wong
    Abstract:

    With the emphasis on low-power design, achieving soft error reliability in Combinational Logic circuits is extremely challenging. In this work, a circuit partitioning technique is used to minimize dynamic power consumption and to mitigate Combinational Logic soft errors. This work shows that for certain circuits, reduction in both power and Combinational Logic soft errors is simultaneously achievable. This is accomplished by partitioning the circuit so that the effective soft error cross section decreases and idle sub-circuits can be disabled to save power. The proposed method was evaluated experimentally using a 4-bit comparator fabricated at the 20-nm bulk CMOS technology node. With the application of the proposed technique, the alpha particle Logic error cross section decreases by 30% compared to a baseline conventional circuit design. Dynamic power reduction of up to 50% is also seen for example circuits.

  • impact of supply voltage and frequency on the soft error rate of Logic circuits
    IEEE Transactions on Nuclear Science, 2013
    Co-Authors: N N Mahatme, B L Bhuva, N J Gaspard, S Jagannathan, T D Loveless, William H Robinson, L W Massengill, S J Wen, R Wong
    Abstract:

    Alpha particle irradiations of 28-nm Combinational Logic and flip-flop circuits under different supply voltage and frequency operating conditions are investigated. Results indicate that while the supply voltage has a strong impact on the alpha particle soft error rate of flip-flops, the Combinational Logic error rate is relatively unaffected by supply voltage variation. Simulations are used to explain the results and highlight the differences between low-LET alpha particle irradiation and heavy-ion irradiation as far as voltage dependence of the Logic soft error rate is concerned. Moreover, frequency has a much stronger impact on the Logic soft error rate as compared to the flip-flop soft error rate. As a result, the frequency at which soft errors from Combinational Logic circuits will exceed errors from flip-flops decreases as the voltage increases. The impact of these observations is discussed in the context of soft-error mitigation strategies.

I. Chatterjee - One of the best experts on this subject based on the ideXlab platform.

  • impact of technology scaling on the Combinational Logic soft error rate
    International Reliability Physics Symposium, 2014
    Co-Authors: N N Mahatme, B L Bhuva, N J Gaspard, S Jagannathan, T D Loveless, L W Massengill, S J Wen, I. Chatterjee, T R Assis, R Wong
    Abstract:

    Experimental results from alpha particle irradiation of 40-nm, 28-nm and 20-nm bulk technology circuits operating in the GHz range suggest that the Combinational Logic soft error rate (SER) per Logic gate decreases with scaling. This rate of decrease for the Logic SER with scaling, however, is not as high as that of the latch SER. As a result, the proportion of Combinational Logic soft errors at the chip level is shown to increase. Results suggest that alpha-particle Logic SER of average sized circuits is about 20% of the latch SER at 20-nm node while it is only 10% at 40-nm at 500 MHz. Moreover, the frequency at which Combinational Logic SER exceeds latch SER decreases with scaling. Factors that influence Logic soft error scaling trends, such as sensitive area, transient pulse-widths and latch characteristics, are estimated through simulations and soft-error rate predictions for future technology nodes are made.

  • Kernel-Based Circuit Partition Approach to Mitigate Combinational Logic Soft Errors
    IEEE Transactions on Nuclear Science, 2014
    Co-Authors: N N Mahatme, B L Bhuva, N J Gaspard, T D Loveless, L W Massengill, S J Wen, T. Assis, I. Chatterjee, W. H. Robinson, R Wong
    Abstract:

    With the emphasis on low-power design, achieving soft error reliability in Combinational Logic circuits is extremely challenging. In this work, a circuit partitioning technique is used to minimize dynamic power consumption and to mitigate Combinational Logic soft errors. This work shows that for certain circuits, reduction in both power and Combinational Logic soft errors is simultaneously achievable. This is accomplished by partitioning the circuit so that the effective soft error cross section decreases and idle sub-circuits can be disabled to save power. The proposed method was evaluated experimentally using a 4-bit comparator fabricated at the 20-nm bulk CMOS technology node. With the application of the proposed technique, the alpha particle Logic error cross section decreases by 30% compared to a baseline conventional circuit design. Dynamic power reduction of up to 50% is also seen for example circuits.

  • Experimental Estimation of the Window of Vulnerability for Logic Circuits
    IEEE Transactions on Nuclear Science, 2013
    Co-Authors: N N Mahatme, B L Bhuva, N J Gaspard, S Jagannathan, T D Loveless, I. Chatterjee, Lloyd W. Massengill, Ronald D. Schrimpf
    Abstract:

    Accurate estimation of single event upset rates for complex Combinational Logic circuits is extremely challenging due to the difficulties involved in calculation of different masking factors. This paper introduces the concept of an effective value of the window of vulnerability which is calculated experimentally for 28 nm bulk CMOS Combinational Logic circuits. Results suggest that the window of vulnerability for different input conditions of the same circuit are similar but that of different circuits could differ. The difference in gate type and topology is identified as the key reason for the differences in window of vulnerability. The window of vulnerability due to alpha particle irradiation for different circuits is between 30-60 ps which compares reasonably with SET pulse-width distributions reported in the past. The effective value of the window of vulnerability could be used to simplify Logic error rate calculations.

  • analysis of soft error rates in Combinational and sequential Logic and implications of hardening for advanced technologies
    International Reliability Physics Symposium, 2010
    Co-Authors: N N Mahatme, B L Bhuva, L W Massengill, J R Ahlbin, I. Chatterjee, R L Shuler
    Abstract:

    Previous results and models have predicted that Combinational Logic errors would dominate over flip-flop errors for the past few technology nodes. However, recent experimental results show very little contribution from Combinational-Logic soft errors to overall soft-error rates. A model that explains the soft error rates as a function of frequency is developed to account for the inconsistency in observed data. Implications for hardening against soft errors for advanced technologies are discussed.