The Experts below are selected from a list of 11577 Experts worldwide ranked by ideXlab platform
Spyros Tragoudas - One of the best experts on this subject based on the ideXlab platform.
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radiation hardened Latch designs for double and triple node upsets
IEEE Transactions on Emerging Topics in Computing, 2017Co-Authors: Adam Watkins, Spyros TragoudasAbstract:As the process feature size continues to scale down, the susceptibility of logic circuits to radiation induced error has increased. This trend has led to the increase in sensitivity of circuits to multi-node upsets. Previously, work has been done to harden Latches against single event upsets (SEU). Currently, there has been a concerted effort to design Latches that are tolerant to double node upsets (DNU) and triple node upsets (TNU). In this paper, we first propose a novel DNU tolerant Latch design. The Latch is designed specifically to provide additional reliability when clock gating is used. Through experimentation, it is shown that the DNU tolerant Latch is 11.3 percent more power efficient than existing Latch designs suited for clock gating. In addition to the DNU tolerant design, we propose the first TNU tolerant Latch. The TNU tolerant Latch is shown to provide superior soft error resiliency while incurring a 40 percent overhead compared to DNU tolerant designs.
N. Ranganathan - One of the best experts on this subject based on the ideXlab platform.
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design of reversible sequential circuits optimizing quantum cost delay and garbage outputs
ACM Journal on Emerging Technologies in Computing Systems, 2010Co-Authors: Himanshu Thapliyal, N. RanganathanAbstract:Reversible logic has shown potential to have extensive applications in emerging technologies such as quantum computing, optical computing, quantum dot cellular automata as well as ultra low power VLSI circuits. Recently, several researchers have focused their efforts on the design and synthesis of efficient reversible logic circuits. In these works, the primary design focus has been on optimizing the number of reversible gates and the garbage outputs. The number of reversible gates is not a good metric of optimization as each reversible gate is of different type and computational complexity, and thus will have a different quantum cost and delay. The computational complexity of a reversible gate can be represented by its quantum cost. Further, delay constitutes an important metric, which has not been addressed in prior works on reversible sequential circuits as a design metric to be optimized. In this work, we present novel designs of reversible sequential circuits that are optimized in terms of quantum cost, delay and the garbage outputs. The optimized designs of several reversible sequential circuits are presented including the D Latch, the JK Latch, the T Latch and the SR Latch, and their corresponding reversible master-slave flip-flop designs. The proposed master-slave flip-flop designs have the special property that they don't require the inversion of the clock for use in the slave Latch. Further, we introduce a novel strategy of cascading a Fredkin gate at the outputs of a reversible Latch to realize the designs of the Fredkin gate based asynchronous set/reset D Latch and the master-slave D flip-flop. Finally, as an example of complex reversible sequential circuits, the reversible logic design of the universal shift register is introduced. The proposed reversible sequential designs were verified through simulations using Verilog HDL and simulation results are presented.
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design of reversible Latches optimized for quantum cost delay and garbage outputs
International Conference on VLSI Design, 2010Co-Authors: Himanshu Thapliyal, N. RanganathanAbstract:Reversible logic has extensive applications in emerging nanotechnologies, such as quantum computing, optical computing, ultra low power VLSI and quantum dot cellular automata. In the existing literature, designs of reversible sequential circuits are presented that are optimized for the number of reversible gates and the garbage outputs. The optimization of the number of reversible gates is not sufficient since each reversible gate is of different computational complexity, and thus will have a different quantum cost and delay. While the computational complexity of a reversible gate can be measured by its quantum cost, the delay of a reversible gate is another parameter that can be optimized during the design of a reversible sequential circuit. In this work, we present novel designs of reversible Latches that are optimized in terms of quantum cost, delay and the garbage outputs. The optimized designs of reversible Latches presented in this work are the D Latch, JK Latch, T Latch and SR Latch.
Adam Watkins - One of the best experts on this subject based on the ideXlab platform.
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radiation hardened Latch designs for double and triple node upsets
IEEE Transactions on Emerging Topics in Computing, 2017Co-Authors: Adam Watkins, Spyros TragoudasAbstract:As the process feature size continues to scale down, the susceptibility of logic circuits to radiation induced error has increased. This trend has led to the increase in sensitivity of circuits to multi-node upsets. Previously, work has been done to harden Latches against single event upsets (SEU). Currently, there has been a concerted effort to design Latches that are tolerant to double node upsets (DNU) and triple node upsets (TNU). In this paper, we first propose a novel DNU tolerant Latch design. The Latch is designed specifically to provide additional reliability when clock gating is used. Through experimentation, it is shown that the DNU tolerant Latch is 11.3 percent more power efficient than existing Latch designs suited for clock gating. In addition to the DNU tolerant design, we propose the first TNU tolerant Latch. The TNU tolerant Latch is shown to provide superior soft error resiliency while incurring a 40 percent overhead compared to DNU tolerant designs.
Himanshu Thapliyal - One of the best experts on this subject based on the ideXlab platform.
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design of reversible sequential circuits optimizing quantum cost delay and garbage outputs
ACM Journal on Emerging Technologies in Computing Systems, 2010Co-Authors: Himanshu Thapliyal, N. RanganathanAbstract:Reversible logic has shown potential to have extensive applications in emerging technologies such as quantum computing, optical computing, quantum dot cellular automata as well as ultra low power VLSI circuits. Recently, several researchers have focused their efforts on the design and synthesis of efficient reversible logic circuits. In these works, the primary design focus has been on optimizing the number of reversible gates and the garbage outputs. The number of reversible gates is not a good metric of optimization as each reversible gate is of different type and computational complexity, and thus will have a different quantum cost and delay. The computational complexity of a reversible gate can be represented by its quantum cost. Further, delay constitutes an important metric, which has not been addressed in prior works on reversible sequential circuits as a design metric to be optimized. In this work, we present novel designs of reversible sequential circuits that are optimized in terms of quantum cost, delay and the garbage outputs. The optimized designs of several reversible sequential circuits are presented including the D Latch, the JK Latch, the T Latch and the SR Latch, and their corresponding reversible master-slave flip-flop designs. The proposed master-slave flip-flop designs have the special property that they don't require the inversion of the clock for use in the slave Latch. Further, we introduce a novel strategy of cascading a Fredkin gate at the outputs of a reversible Latch to realize the designs of the Fredkin gate based asynchronous set/reset D Latch and the master-slave D flip-flop. Finally, as an example of complex reversible sequential circuits, the reversible logic design of the universal shift register is introduced. The proposed reversible sequential designs were verified through simulations using Verilog HDL and simulation results are presented.
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design of reversible Latches optimized for quantum cost delay and garbage outputs
International Conference on VLSI Design, 2010Co-Authors: Himanshu Thapliyal, N. RanganathanAbstract:Reversible logic has extensive applications in emerging nanotechnologies, such as quantum computing, optical computing, ultra low power VLSI and quantum dot cellular automata. In the existing literature, designs of reversible sequential circuits are presented that are optimized for the number of reversible gates and the garbage outputs. The optimization of the number of reversible gates is not sufficient since each reversible gate is of different computational complexity, and thus will have a different quantum cost and delay. While the computational complexity of a reversible gate can be measured by its quantum cost, the delay of a reversible gate is another parameter that can be optimized during the design of a reversible sequential circuit. In this work, we present novel designs of reversible Latches that are optimized in terms of quantum cost, delay and the garbage outputs. The optimized designs of reversible Latches presented in this work are the D Latch, JK Latch, T Latch and SR Latch.
Mekie Joycee - One of the best experts on this subject based on the ideXlab platform.
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Upset hardened Latch as data synchronizer
IEEE, 2017Co-Authors: Kumari Neha, Mekie JoyceeAbstract:Upset hardened dual-interlocked cell (DICE) [1] has found an important place in circuits for space applications due to its ability to mitigate single event upsets (SEUs). In this paper, we show that DICE Latch/flip-flop exhibits better immunity to metastability compared to D flip-flop, and can be used as data synchronizer. Metastablity constant (?), whose inverse captures the ability of the Latch to exit from metastable state is about one-half in DICE compared to a similar sized standard Latch. This would mean an improvement of 7x in mean-time between failure (MTBF) due to metastability. We have simulated both DICE and D flip-flops designed in different technology nodes-180nm, 130nm, 65nm, and 40nm for planar devices and 20nm, 16nm, 14nm, 10nm and 7nm for FinFET devices along with process variations. We have done pre and post-layout simulations of DICE and D flip-flops taking into account process corners variations. We report that DICE exhibits better metastability hardness compared to D flip-flop across all technology nodes, except at 7nm. We also report that in all the cases ? of DICE flip-flop is lower than that of D flip-flop.by Neha Kumari, and Joycee Meki
