The Experts below are selected from a list of 174789 Experts worldwide ranked by ideXlab platform
Limi Xiao - One of the best experts on this subject based on the ideXlab platform.
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Semi-User-Level Communication Architecture
2015Co-Authors: Da Meng, Limi XiaoAbstract:This paper introduces semi-user-level Communication Architecture, a new high-performance light-weighted com-munication Architecture for inter-node Communication of clusters. Different from traditional kernel-level network-ing Architecture and user-level Communication architec-ture, semi-user-level Communication Architecture removes OS kernel from its message-receiving path while reserves an OS trapping on its message-sending path. No interrupt handling is needed. This new Communication Architecture doesn’t support user-level access to network interface. It provides good portability, security, and support for hetero-geneous networking environment and usage of large mem-ory. Semi-user-level Communication Architecture has been implemented on a SMP workstation cluster system called DAWNING-3000, which is interconnected through Myrinet. Communication performance results are given and over-head distribution is analyzed. 1
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IPDPS - Semi-user-level Communication Architecture
Proceedings 16th International Parallel and Distributed Processing Symposium, 2002Co-Authors: Dan Meng, Limi XiaoAbstract:This paper introduces semi-user-level Communication Architecture, a new high-performance light-weighted Communication Architecture for inter-node Communication of clusters. Different from traditional kernel-level networking Architecture and user-level Communication Architecture, semi-user-level Communication Architecture removes OS kernel from its message-receiving path while reserves an OS trapping on its message-sending path. No interrupt handling is needed. This new Communication Architecture doesn't support user-level access to network interface. It provides good portability, security, and support for heterogeneous networking environment and usage of large memory. Semi-user-level Communication Architecture has been implemented on a SMP workstation cluster system called DAWNING-3000, which is interconnected through Myrinet. Communication performance results are given and overhead distribution is analyzed.
Anand Raghunathan - One of the best experts on this subject based on the ideXlab platform.
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The LOTTERYBUS on-chip Communication Architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2006Co-Authors: Kanishka Lahiri, Anand Raghunathan, Ganesh LakshminarayanaAbstract:On-chip Communication Architectures play an important role in determining the overall performance of System-on-Chip (SoC) designs. Communication Architectures should be flexible so as to offer high performance over a wide range of traffic characteristics. In particular, the resource sharing mechanism of the Communication Architecture, which determines how the often-conflicting requirements of different components are served, is of utmost importance. Conventional SoC Architectures typically employ priority or time-division multiple-access (TDMA)-based Communication Architectures. However, these techniques are often inadequate. In the former, low-priority components may suffer from starvation, while in the latter, depending on the request profile, high-priority traffic may be subject to large latencies. This paper presents LOTTERYBUS, a high-performance SoC Communication Architecture based on new randomized on-chip Communication protocols that addresses the shortcomings mentioned above. LOTTERYBUS provides each SoC component with a flexible, proportional, and probabilistically guaranteed share of the on-chip Communication bandwidth. We present two variants of LOTTERYBUS. In the first variant, its architectural parameters are statically configured, leading to relatively low hardware overhead and design complexity. In the second variant, these parameters are allowed to vary dynamically, enabling more sophisticated use of LOTTERYBUS, at additional hardware cost. We have performed experiments to investigate the performance of LOTTERYBUS across a range of Communication traffic characteristics. We have used LOTTERYBUS in designing a 4times4 ATM switch subsystem, and have compared its performance with conventional Architectures. The results show that LOTTERYBUS provides fine-grained control over bandwidth allocation, and also provides significant reduction in average transaction latencies (up to 85%) compared to conventional Architectures. Hardware implementations using a commercial 0.15-mum cell-based library indicate that the advantages provided by LOTTERYBUS are accompanied by modest hardware overheads compared to conventional Architectures
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seca security enhanced Communication Architecture
Compilers Architecture and Synthesis for Embedded Systems, 2005Co-Authors: Joel Coburn, S Ravi, Anand Raghunathan, Srimat T ChakradharAbstract:In this work, we propose and investigate the idea of enhancing a System-on-Chip (SoC) Communication Architecture (the fabric that integrates system components and carries the Communication traffic between them) to facilitate higher security. We observe that a wide range of common security attacks are manifested as abnormalities in the system-level Communication traffic. Therefore, the Communication Architecture, with its global system-level visibility, can be used to detect them. The Communication Architecture can also effectively react to security attacks by disallowing the offending Communication transactions, or by notifying appropriate components of a security violation. We describe the general principles involved in a security-enhanced Communication Architecture (SECA) and show how several security objectives can be encoded in terms of policies that govern the inter-component Communication traffic. We detail the implementation of SECA in the context of a popular commercial on-chip bus Architecture (the AMBA Architecture from ARM) through a combination of a centralized security enforcement module, and enhancements to the bus interfaces of system components. We illustrate how SECA can be used to enhance embedded system security in several application scenarios. A simple instance of SECA has been implemented in a commercial application processor SoC for mobile phones. We provide results of experiments performed to validate the proposed concepts through system-level simulation, and evaluate their overheads through hardware implementation using a commercial design flow.
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CASES - SECA: security-enhanced Communication Architecture
Proceedings of the 2005 international conference on Compilers architectures and synthesis for embedded systems - CASES '05, 2005Co-Authors: Joel Coburn, S Ravi, Anand Raghunathan, Srimat T ChakradharAbstract:In this work, we propose and investigate the idea of enhancing a System-on-Chip (SoC) Communication Architecture (the fabric that integrates system components and carries the Communication traffic between them) to facilitate higher security. We observe that a wide range of common security attacks are manifested as abnormalities in the system-level Communication traffic. Therefore, the Communication Architecture, with its global system-level visibility, can be used to detect them. The Communication Architecture can also effectively react to security attacks by disallowing the offending Communication transactions, or by notifying appropriate components of a security violation. We describe the general principles involved in a security-enhanced Communication Architecture (SECA) and show how several security objectives can be encoded in terms of policies that govern the inter-component Communication traffic. We detail the implementation of SECA in the context of a popular commercial on-chip bus Architecture (the AMBA Architecture from ARM) through a combination of a centralized security enforcement module, and enhancements to the bus interfaces of system components. We illustrate how SECA can be used to enhance embedded system security in several application scenarios. A simple instance of SECA has been implemented in a commercial application processor SoC for mobile phones. We provide results of experiments performed to validate the proposed concepts through system-level simulation, and evaluate their overheads through hardware implementation using a commercial design flow.
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Design of high-performance system-on-chips using Communication Architecture tuners
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2004Co-Authors: Kanishka Lahiri, Anand Raghunathan, Ganesh Lakshminarayana, Sujit DeyAbstract:In this paper, we present a methodology for the design of high-performance system-on-chip Communication Architectures. The approach is based on the addition of a layer of circuitry called the Communication Architecture tuner (CAT) layer around an existing Communication Architecture topology. The added layer provides a system with the capability of adapting to runtime variability in the Communication needs of its constituent components. For example, more critical data may be handled differently, leading to lower Communication latencies. The CAT associated with each component monitors its internal state, analyzes the Communication transactions it generates, and "predicts" the relative importance of the transactions in terms of their impact on system-level performance metrics. It then configures the protocol parameters of the underlying Communication Architecture (e.g., priorities, burst modes, etc.) to best suit the system's changing Communication needs. We illustrate the issues and tradeoffs involved in the design of CAT-based Communication Architectures, and present algorithms that automate the key steps. Experiments with example systems indicate that performance metrics (e.g., number of missed deadlines, average processing time) for systems with CAT-based Communication Architectures are significantly (sometimes over an order of magnitude) better than those with conventional Communication Architectures.
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lotterybus a new high performance Communication Architecture for system on chip designs
Design Automation Conference, 2001Co-Authors: Kanishka Lahiri, Anand Raghunathan, Ganesh LakshminarayanaAbstract:This paper presents Lotterybus, a novel high-performance Communication Architecture for system-on-chip (SoC) designs. The Lotterybus Architecture was designed to address the following limitations of current Communication Architectures: (i) lack of control over the allocation of Communication bandwidth to different system components or data flows ( e.g. , in static priority based shared buses), leading to starvation of lower priority components in some situations, and (ii) significant latencies resulting from variations in the time-profile of the Communication requests ( e.g. , in time division multiplexed access (TDMA) based Architectures), sometimes leading to larger latencies for high-priority Communications. We present two variations of Lotterybus: the first is a low overhead Architecture with statically configured parameters, while the second variant is a more sophisticated Architecture, in which values of the architectural parameters are allowed to vary dynamically. Our experiments investigate the performance of the Lotterybus Architecture across a wide range of Communication traffic characteristics. In addition, we also analyze its performance in a 4x4 ATM switch sub-system design. The results demonstrate that the Lotterybus Architecture is (i) capable of providing the designer with fine grained control over the bandwidth allocated to each SoC component or data flow, and (ii) well suited to provide high priority Communication traffic with low latencies (we observed upto 85.4\% reduction in Communication latencies over conventional on-chip Communication Architectures).
Srimat T Chakradhar - One of the best experts on this subject based on the ideXlab platform.
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seca security enhanced Communication Architecture
Compilers Architecture and Synthesis for Embedded Systems, 2005Co-Authors: Joel Coburn, S Ravi, Anand Raghunathan, Srimat T ChakradharAbstract:In this work, we propose and investigate the idea of enhancing a System-on-Chip (SoC) Communication Architecture (the fabric that integrates system components and carries the Communication traffic between them) to facilitate higher security. We observe that a wide range of common security attacks are manifested as abnormalities in the system-level Communication traffic. Therefore, the Communication Architecture, with its global system-level visibility, can be used to detect them. The Communication Architecture can also effectively react to security attacks by disallowing the offending Communication transactions, or by notifying appropriate components of a security violation. We describe the general principles involved in a security-enhanced Communication Architecture (SECA) and show how several security objectives can be encoded in terms of policies that govern the inter-component Communication traffic. We detail the implementation of SECA in the context of a popular commercial on-chip bus Architecture (the AMBA Architecture from ARM) through a combination of a centralized security enforcement module, and enhancements to the bus interfaces of system components. We illustrate how SECA can be used to enhance embedded system security in several application scenarios. A simple instance of SECA has been implemented in a commercial application processor SoC for mobile phones. We provide results of experiments performed to validate the proposed concepts through system-level simulation, and evaluate their overheads through hardware implementation using a commercial design flow.
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CASES - SECA: security-enhanced Communication Architecture
Proceedings of the 2005 international conference on Compilers architectures and synthesis for embedded systems - CASES '05, 2005Co-Authors: Joel Coburn, S Ravi, Anand Raghunathan, Srimat T ChakradharAbstract:In this work, we propose and investigate the idea of enhancing a System-on-Chip (SoC) Communication Architecture (the fabric that integrates system components and carries the Communication traffic between them) to facilitate higher security. We observe that a wide range of common security attacks are manifested as abnormalities in the system-level Communication traffic. Therefore, the Communication Architecture, with its global system-level visibility, can be used to detect them. The Communication Architecture can also effectively react to security attacks by disallowing the offending Communication transactions, or by notifying appropriate components of a security violation. We describe the general principles involved in a security-enhanced Communication Architecture (SECA) and show how several security objectives can be encoded in terms of policies that govern the inter-component Communication traffic. We detail the implementation of SECA in the context of a popular commercial on-chip bus Architecture (the AMBA Architecture from ARM) through a combination of a centralized security enforcement module, and enhancements to the bus interfaces of system components. We illustrate how SECA can be used to enhance embedded system security in several application scenarios. A simple instance of SECA has been implemented in a commercial application processor SoC for mobile phones. We provide results of experiments performed to validate the proposed concepts through system-level simulation, and evaluate their overheads through hardware implementation using a commercial design flow.
Joel Coburn - One of the best experts on this subject based on the ideXlab platform.
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seca security enhanced Communication Architecture
Compilers Architecture and Synthesis for Embedded Systems, 2005Co-Authors: Joel Coburn, S Ravi, Anand Raghunathan, Srimat T ChakradharAbstract:In this work, we propose and investigate the idea of enhancing a System-on-Chip (SoC) Communication Architecture (the fabric that integrates system components and carries the Communication traffic between them) to facilitate higher security. We observe that a wide range of common security attacks are manifested as abnormalities in the system-level Communication traffic. Therefore, the Communication Architecture, with its global system-level visibility, can be used to detect them. The Communication Architecture can also effectively react to security attacks by disallowing the offending Communication transactions, or by notifying appropriate components of a security violation. We describe the general principles involved in a security-enhanced Communication Architecture (SECA) and show how several security objectives can be encoded in terms of policies that govern the inter-component Communication traffic. We detail the implementation of SECA in the context of a popular commercial on-chip bus Architecture (the AMBA Architecture from ARM) through a combination of a centralized security enforcement module, and enhancements to the bus interfaces of system components. We illustrate how SECA can be used to enhance embedded system security in several application scenarios. A simple instance of SECA has been implemented in a commercial application processor SoC for mobile phones. We provide results of experiments performed to validate the proposed concepts through system-level simulation, and evaluate their overheads through hardware implementation using a commercial design flow.
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CASES - SECA: security-enhanced Communication Architecture
Proceedings of the 2005 international conference on Compilers architectures and synthesis for embedded systems - CASES '05, 2005Co-Authors: Joel Coburn, S Ravi, Anand Raghunathan, Srimat T ChakradharAbstract:In this work, we propose and investigate the idea of enhancing a System-on-Chip (SoC) Communication Architecture (the fabric that integrates system components and carries the Communication traffic between them) to facilitate higher security. We observe that a wide range of common security attacks are manifested as abnormalities in the system-level Communication traffic. Therefore, the Communication Architecture, with its global system-level visibility, can be used to detect them. The Communication Architecture can also effectively react to security attacks by disallowing the offending Communication transactions, or by notifying appropriate components of a security violation. We describe the general principles involved in a security-enhanced Communication Architecture (SECA) and show how several security objectives can be encoded in terms of policies that govern the inter-component Communication traffic. We detail the implementation of SECA in the context of a popular commercial on-chip bus Architecture (the AMBA Architecture from ARM) through a combination of a centralized security enforcement module, and enhancements to the bus interfaces of system components. We illustrate how SECA can be used to enhance embedded system security in several application scenarios. A simple instance of SECA has been implemented in a commercial application processor SoC for mobile phones. We provide results of experiments performed to validate the proposed concepts through system-level simulation, and evaluate their overheads through hardware implementation using a commercial design flow.
Dan Meng - One of the best experts on this subject based on the ideXlab platform.
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IPDPS - Semi-user-level Communication Architecture
Proceedings 16th International Parallel and Distributed Processing Symposium, 2002Co-Authors: Dan Meng, Limi XiaoAbstract:This paper introduces semi-user-level Communication Architecture, a new high-performance light-weighted Communication Architecture for inter-node Communication of clusters. Different from traditional kernel-level networking Architecture and user-level Communication Architecture, semi-user-level Communication Architecture removes OS kernel from its message-receiving path while reserves an OS trapping on its message-sending path. No interrupt handling is needed. This new Communication Architecture doesn't support user-level access to network interface. It provides good portability, security, and support for heterogeneous networking environment and usage of large memory. Semi-user-level Communication Architecture has been implemented on a SMP workstation cluster system called DAWNING-3000, which is interconnected through Myrinet. Communication performance results are given and overhead distribution is analyzed.