The Experts below are selected from a list of 72 Experts worldwide ranked by ideXlab platform

Kenneth B. Kent - One of the best experts on this subject based on the ideXlab platform.

  • An OpenMP-based circuit design tool: Customizable bit-width
    2009 IEEE Pacific Rim Conference on Communications Computers and Signal Processing, 2009
    Co-Authors: Timothy F. Beatty, Eric Aubanel, Kenneth B. Kent
    Abstract:

    As transistor density grows, increasingly complex hardware designs may be implemented. In order to manage this complexity, hardware design can be performed at a higher level of abstraction. High level synthesis enables the automatic conversion of algorithms into hardware implementations, abstracting away the underlying complexities of hardware from the designer. A number of high level synthesis tools have recently been developed, including an OpenMP to HandelC translator. Improvements to the translator, including a new Compiler Directive allowing customizable register width, are described. Using a set of benchmark tests, the OpenMP to HandelC translator is evaluated on several criteria, with the goal of evaluating the variable bit-width effects and identifying further areas for improvement.

  • FPGA - Customizable bit-width in an OpenMP-based circuit design tool
    Proceeding of the ACM SIGDA international symposium on Field programmable gate arrays - FPGA '09, 2009
    Co-Authors: Timothy F. Beatty, Eric Aubanel, Kenneth B. Kent
    Abstract:

    As transistor density grows, increasingly complex hardware designs are implemented. In order to manage this complexity, hardware design can be performed at a higher level of abstraction. High level synthesis enables the automatic conversion of algorithms into hardware implementations, abstracting away the underlying complexities of hardware from the designer. A number of high level synthesis tools have recently been developed, including an OpenMP to Handel-C translator. Improvements to the translator, including a new Compiler Directive allowing customizable register width, are described. Using a set of benchmark tests, the OpenMP to Handel-C translator is evaluated on several criteria, with the goal of evaluating the variable bit-width effects and identifying further areas for improvement.

Qin Jiang - One of the best experts on this subject based on the ideXlab platform.

Timothy F. Beatty - One of the best experts on this subject based on the ideXlab platform.

  • An OpenMP-based circuit design tool: Customizable bit-width
    2009 IEEE Pacific Rim Conference on Communications Computers and Signal Processing, 2009
    Co-Authors: Timothy F. Beatty, Eric Aubanel, Kenneth B. Kent
    Abstract:

    As transistor density grows, increasingly complex hardware designs may be implemented. In order to manage this complexity, hardware design can be performed at a higher level of abstraction. High level synthesis enables the automatic conversion of algorithms into hardware implementations, abstracting away the underlying complexities of hardware from the designer. A number of high level synthesis tools have recently been developed, including an OpenMP to HandelC translator. Improvements to the translator, including a new Compiler Directive allowing customizable register width, are described. Using a set of benchmark tests, the OpenMP to HandelC translator is evaluated on several criteria, with the goal of evaluating the variable bit-width effects and identifying further areas for improvement.

  • FPGA - Customizable bit-width in an OpenMP-based circuit design tool
    Proceeding of the ACM SIGDA international symposium on Field programmable gate arrays - FPGA '09, 2009
    Co-Authors: Timothy F. Beatty, Eric Aubanel, Kenneth B. Kent
    Abstract:

    As transistor density grows, increasingly complex hardware designs are implemented. In order to manage this complexity, hardware design can be performed at a higher level of abstraction. High level synthesis enables the automatic conversion of algorithms into hardware implementations, abstracting away the underlying complexities of hardware from the designer. A number of high level synthesis tools have recently been developed, including an OpenMP to Handel-C translator. Improvements to the translator, including a new Compiler Directive allowing customizable register width, are described. Using a set of benchmark tests, the OpenMP to Handel-C translator is evaluated on several criteria, with the goal of evaluating the variable bit-width effects and identifying further areas for improvement.

Zhao Rong-cai - One of the best experts on this subject based on the ideXlab platform.

Ranjit Noronha - One of the best experts on this subject based on the ideXlab platform.

  • D.K.: Improving scalability of OpenMP applications on multi-core systems using large page support
    2007
    Co-Authors: Ranjit Noronha
    Abstract:

    Modern multi-core architectures have become popular because of the limitations of deep pipelines and heating and power concerns. Some of these multi-core architectures such as the Intel Xeon have the ability to run several threads on a single core. The OpenMP standard for Compiler Directive based shared memory programming allows the developer an easy path to writing multi-threaded programs and is a natural fit for multi-core architectures. The OpenMP standard uses loop parallelism as a basis for work division among multiple threads. These loops usually use arrays in their computation with different data distributions and access patterns. The performance of accesses to these arrays may be impacted by the underlying page size depending on the frequency and strides of these accesses. In this paper, we discuss the issues and potential benefits from using large pages for OpenMP applications. We design an OpenMP implementation capable of using large pages and evaluate the impact of using large page support available in most modern processors on the performance and scalability of parallel OpenMP applications. Results show an improvement in performance of up to 25 % for some applications. It also helps improve the scalability of these applications.

  • Improving Scalability of OpenMP Applications on Multi-core Systems Using Large Page Support
    2007
    Co-Authors: Ranjit Noronha
    Abstract:

    Modern multicore architectures have become popular because of the limitations of deep pipelines and heating and power concerns. Some of these multicore architectures such as the Intel Xeon have the ability to run several threads on a single core. The OpenMP standard for Compiler Directive based shared memory programming allows the developer an easy path to writing multithreaded programs and is a natural fit for multicore architectures. The OpenMP standard uses loop parallelism as a basis for work division among multiple threads. These loops usually use arrays in their computation with different data distributions and access patterns. The performance of accesses to these arrays may be dependent on the underlying page size depending on the frequency and strides of these accesses. In this paper, we discuss the issues and potential benefits from using large pages for OpenMP applications. We design an OpenMP implementation capable of using large pages and evaluate the impact of using large page support available in most modern processors on the performance and scalability of parallel OpenMP applications. Results show an improvement in performance of up to 25 % for some applications. It also helps improve the scalability of these applications