The Experts below are selected from a list of 27 Experts worldwide ranked by ideXlab platform

Chiphong Chang - One of the best experts on this subject based on the ideXlab platform.

  • a power delay efficient hybrid carry lookahead carry select based redundant binary to two s Complement converter
    IEEE Transactions on Circuits and Systems I-regular Papers, 2008
    Co-Authors: Yajuan He, Chiphong Chang
    Abstract:

    This paper presents an efficient reverse converter for transForming the redundant binary (RB) representation into two's Complement Form. The hierarchical expansion of the carry equation for the reverse conversion algorithm creates a regular multilevel structure, from which a high-speed hybrid carry-lookahead/carry-select (CLA/CSL) architecture is proposed to fully exploit the redundancy of RB encoding for VLSI efficient implementation. The optimally designed CSL sections interleaved evenly in the mixed-radix CLA network to boost the perFormance of the reverse converter well above those designed based on a homogeneous type of carry propagation adder. The logical effort characterization captures the effect of circuit's fan-in, fan-out and transistor sizing on perFormance, and the evaluation shows that our proposed architecture leads to the fastest design. A 64-bit transistor-level circuit implementation of our proposed reverse converter and that of its most competitive contender were simulated to validate the logical effort delay model. The pre- and post-layout HSPICE simulation results reveal that our new converter expends at least two times less energy (power-delay product) than the competitor circuit and is capable of completing a 64-bit conversion in 829 ps and dissipates merely 5.84 mW at a data rate of 1 GHz and a supply voltage of 1.8 V in TSMC 0.18-mum CMOS technology.

Yajuan He - One of the best experts on this subject based on the ideXlab platform.

  • a power delay efficient hybrid carry lookahead carry select based redundant binary to two s Complement converter
    IEEE Transactions on Circuits and Systems I-regular Papers, 2008
    Co-Authors: Yajuan He, Chiphong Chang
    Abstract:

    This paper presents an efficient reverse converter for transForming the redundant binary (RB) representation into two's Complement Form. The hierarchical expansion of the carry equation for the reverse conversion algorithm creates a regular multilevel structure, from which a high-speed hybrid carry-lookahead/carry-select (CLA/CSL) architecture is proposed to fully exploit the redundancy of RB encoding for VLSI efficient implementation. The optimally designed CSL sections interleaved evenly in the mixed-radix CLA network to boost the perFormance of the reverse converter well above those designed based on a homogeneous type of carry propagation adder. The logical effort characterization captures the effect of circuit's fan-in, fan-out and transistor sizing on perFormance, and the evaluation shows that our proposed architecture leads to the fastest design. A 64-bit transistor-level circuit implementation of our proposed reverse converter and that of its most competitive contender were simulated to validate the logical effort delay model. The pre- and post-layout HSPICE simulation results reveal that our new converter expends at least two times less energy (power-delay product) than the competitor circuit and is capable of completing a 64-bit conversion in 829 ps and dissipates merely 5.84 mW at a data rate of 1 GHz and a supply voltage of 1.8 V in TSMC 0.18-mum CMOS technology.

D Radhakrishnan - One of the best experts on this subject based on the ideXlab platform.

  • fast redundant binary partial product generators for booth multiplication
    Midwest Symposium on Circuits and Systems, 2007
    Co-Authors: Bijoy A Jose, D Radhakrishnan
    Abstract:

    The use of signed-digit number systems in arithmetic circuits has the advantage of constant time addition irrespective of word length. In this paper, we present the design of a binary signed-digit partial product generator, which expresses each normal binary operand in one's Complement Form with an extra bit denoting the sign bit of the operand. The carry free nature of RBAs is exploited to add the extra bits with the partial products, without using additional adder stages. This technique allows RB encoding to be used in multipliers with operand widths which are perfect powers of two, without increasing the delay of partial product accumulation. The proposed partial product generator achieves the highest reduction in the number of partial products for a radix-4 multiplier (78%), by combining advantages of RB encoding with RB addition. The proposed partial product generator together with a set of fast redundant binary adder stages configured in a binary tree fashion can result in the design of high perFormance multipliers.

Hendrik Rogier - One of the best experts on this subject based on the ideXlab platform.

  • on the schur Complement Form of the dirichlet to neumann operator
    Wave Motion, 2008
    Co-Authors: Luc Knockaert, D De Zutter, G Lippens, Hendrik Rogier
    Abstract:

    Abstract The Dirichlet-to-Neumann operator relates the values of the normal derivative of a scalar field to the values of the field itself on the boundary of a simply connected domain. Although it is easy to prove analytically that the Dirichlet-to-Neumann operator is self-adjoint, the discretization of the pertinent Green’s integral equation by means of the usual Galerkin approach generally results in a non-symmetric matrix representation of that operator. In this paper we remedy this by means of a Hamiltonian Schur Complement method and compare it with other symmetrization approaches. It is also shown that the problem of E-wave scattering by a lossy dielectric cylinder can be nicely simplified by means of the Dirichlet-to-Neumann operator. A numerical Galerkin implementation demonstrates the strength and versatility of the present approach.

Apostolou, Nikolaos E. - One of the best experts on this subject based on the ideXlab platform.

  • Design and evaluation of serial-parallel Modified Booth multiplier schemes
    2012
    Co-Authors: Αποστόλου, Νικόλαος Ε., Apostolou, Nikolaos E.
    Abstract:

    121 σ.Ο σκοπός της παρούσας διπλωματικής εργασίας ήταν η σχεδίαση διαφόρων τοπολογιών σειριακών-παράλληλων πολλαπλασιαστών και η διερεύνησή τους ως προς τις επιδόσεις τους και ειδικότερα ως προς τις δυνατότητές τους στην επίτευξη λειτουργίας με χαμηλή κατανάλωση. Υλοποιήθηκαν δύο νέες σχεδιαστικές ιδέες. Η πρώτη αφορά την χρήση μιας γενικευμένης μορφής αναπαράστασης «σωσίματος – κρατουμένου» (carry – save) για τα ενδιάμεσα στάδια των υπολογισμών, με σκοπό την ελάττωση των απαιτούμενων καταχωρητών, ενώ η δεύτερη αφορά την χρήση της κανονικής αναπαράστασης προσημασμένου ψηφίου (canonical signed digit representation) σε συνδυασμό με την κωδικοποίηση Modified-Booth, με σκοπό την παραγωγή όσο το δυνατόν λιγότερων μη μηδενικών μερικών γινομένων. Σχεδιάστηκαν κυκλώματα πολλαπλασιασμού, τα οποία λαμβάνουν δεδομένα σε μορφή συμπληρώματος του δύο, με την μια είσοδο παράλληλα (πολλαπλασιαστέος) και την άλλη σειριακά (πολλαπλασιαστής), και μετασχηματίζουν την μία είσοδό τους (σειριακή) σύμφωνα με την μέθοδο MacSorley-Booth (Modified Booth) για την ελάττωση των προς άθροιση μερικών γινομένων. Μελετήθηκαν αρχιτεκτονικές με διαφορετικό μήκος ενδιάμεσης λέξης (radix-2 ως και radix-8) σκοπεύοντας πρωτίστως στην ελάττωση της δυναμικής κατανάλωσης. Επίσης, διερευνήθηκαν διαφορετικές κωδικοποιήσεις Modified Booth και οι επιπτώσεις τους στην δυναμική κατανάλωση του κυκλώματος. Πιο συγκεκριμένα, υλοποιήθηκε σε γλώσσα Verilog μια σειρά σειριακών-παράλληλων πολλαπλασιαστών Modified Booth σε radix-2, radix-4 και radix-8 και σε μήκη λέξεως 8 ως 64 bits. Η λειτουργία τους προσομοιώθηκε με βάση μια standard cell CMOS βιβλιοθήκη 90nm της Artisan. Τα αποτελέσματα καθυστέρησης (critical path), κατανάλωσης και επιφανείας συγκρίθηκαν με έναν απλό σειριακό-παράλληλο πολλαπλασιαστή και με έναν, παρόμοιας λογικής, δενδρικό παράλληλο πολλαπλασιαστή της Designware (tree multiplier).The scope of this thesis was the design of various serial-parallel multiplier schemes, as well as the investigation of their perFormance, especially as far as their energy consumption is concerned. The designs created, were based on two novelties. The first one is the use of a generalized “carry-save” scheme, which is used in the intermediate steps of the calculations in order to reduce the number of registers needed, while the second is the use of the “canonical signed digit representation” applied on the Modified-Booth encoding scheme, in order to minimize the number of the non-zero partial products created. The designed multiplier schemes receive data in two’s Complement Form. The multiplier is in parallel series Form while the multiplicand is in bit-series Form. In all designs the serial input is transFormed according to the MacSoreley-Booth method (Modified Booth) in order to reduce the number of partial products which will be added. Various radix schemes were studied (radix-2 to radix-8), targeting mainly to the reduction of their dynamic power consumption. More specifically, we designed a series of Modified-Booth serial-parallel multipliers using Verilog HDL. The designs include radix-2, radix-4 and radix-8 schemes, while the inputs can be 8, 16, 24, 32, 48, or 64 bits wide. The designs were synthesized and simulated using a 90nm standard cell CMOS library by Artisan. The energy, delay and area results are presented, compared to a simple (radix-1) serial-parallel multiplier as well as a parallel tree-multiplier synthesized using the Designware library.Νικόλαος Ε. Αποστόλο