The Experts below are selected from a list of 519495 Experts worldwide ranked by ideXlab platform
Vassilis Paliouras - One of the best experts on this subject based on the ideXlab platform.
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A low-complexity high-radix RNS multiplier
IEEE Transactions on Circuits and Systems I: Regular Papers, 2009Co-Authors: Ioannis Kouretas, Vassilis PaliourasAbstract:A graph-based technique is introduced for the design of a class of residue arithmetic Multipliers, as well as a family of new high-radix digit adders. A proposed design technique derives simple high-radix modulo-r n Multipliers by optimally selecting among the variety of introduced digit adders the ones that compose a minimal-area multiplier. The proposed technique minimizes multiplier complexity by selecting digit adders that observe the constraints imposed on the maximum values of the various intermediate digits. The proposed technique leads to significant area and time improvements over previously published architectures for practical modulus cases.
Ioannis Kouretas - One of the best experts on this subject based on the ideXlab platform.
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A low-complexity high-radix RNS multiplier
IEEE Transactions on Circuits and Systems I: Regular Papers, 2009Co-Authors: Ioannis Kouretas, Vassilis PaliourasAbstract:A graph-based technique is introduced for the design of a class of residue arithmetic Multipliers, as well as a family of new high-radix digit adders. A proposed design technique derives simple high-radix modulo-r n Multipliers by optimally selecting among the variety of introduced digit adders the ones that compose a minimal-area multiplier. The proposed technique minimizes multiplier complexity by selecting digit adders that observe the constraints imposed on the maximum values of the various intermediate digits. The proposed technique leads to significant area and time improvements over previously published architectures for practical modulus cases.
Muhammad Shafique - One of the best experts on this subject based on the ideXlab platform.
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Low Power Digital Clock Multipliers for Battery-Operated Internet of Things (IoT) Devices
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018Co-Authors: Faiq Khalid, Sunil Nanjiani, Syed Rafay Hasan, Osman Hasan, Falah Awwad, Muhammad ShafiqueAbstract:The recent advancements in system-on-chip (SoC) and network-on-chip (NoC) have enormously increased the number of on-chip frequency domains that are originating from multiple on-chip clock sources. In modern battery-operated internet of things (IoT) devices, limited power budget and requirement for complex clock distribution schemes increases the usage clock Multipliers. These multiple clock signal requirements are usually catered for by using frequency Multipliers with clock generators. However, most of these Multipliers are based on analog components that require a customized layout, involve timing uncertainties, and are power hungry and highly prone to mismatches in the process variations and environmental changes. Moreover, in modern battery-operated smart devices for IoT have very limited power budget, which makes the design of clock Multipliers even more challenging. To address these issues, we propose a delay-based digital frequency multiplier, which uses 2-input XNOR gates and a true single-phase clock (TSPC) flip-flop because of pulse generation and edge detection properties, respectively. The proposed multiplier is based on the digital components, therefore, it reduces the power consumption significantly, i.e., 1.6mW, which is almost 50% lesser than other low power state-of-the-art designs. Moreover, it can operate for a wide range of input frequencies, ∼400MHz to 1GHz. The Monte-Carlo simulation results are very promising as they indicate the robustness of the design against process and environmental variations.
Michael Woodford - One of the best experts on this subject based on the ideXlab platform.
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simple analytics of the government expenditure multiplier
American Economic Journal: Macroeconomics, 2011Co-Authors: Michael WoodfordAbstract:This paper explains the key factors that determine the output multiplier of government purchases in New Keynesian models, through a series of simple examples that can be solved analytically. Sticky prices or wages allow for larger Multipliers than in a neoclassical model, though the size of the multiplier depends crucially on the monetary policy response. A multiplier well in excess of one is possible when monetary policy is constrained by the zero lower bound, and in this case welfare increases if government purchases expand to partially fill the output gap that arises from the inability to lower interest rates. (JEL E12, E23, E32, E62, H20, H50)
Bogdan Pasca - One of the best experts on this subject based on the ideXlab platform.
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FPL - Extracting INT8 Multipliers from INT18 Multipliers
2019 29th International Conference on Field Programmable Logic and Applications (FPL), 2019Co-Authors: Martin Langhammer, Bogdan Pasca, Gregg Baeckler, Sergey GribokAbstract:With the advent of machine learning as perhaps the most high-profile application area for FPGAs, there is a compelling reason to improve the provision of smaller precision arithmetic on these devices. INT8 is commonly used for AI inferencing, and along with some additional soft logic for exponent handling, can be an effective solution for training as well. This paper describes techniques for efficiently extracting INT8 Multipliers from commonly available INT18 Multipliers found in many modern FPGAs. A small amount of soft logic - as little as 7 ALMs per INT8 multiplier - is required to provide pre or post multiplier correction to calculate two INT8 multiplies from a single 18x18 multiplier. We present two configurations for both signed and unsigned representations where two multiplications share one input operand. In addition to the individual INT8 variants, we present full device cases of 22,400 INT8 Multipliers organized as DOT32 product arrays, with the soft logic tightly bound to the INT18 based DSP Blocks. A majority of the soft logic and routing in the device is left untouched, and available for application development.
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Multipliers for floating point double precision and beyond on fpgas
ACM Sigarch Computer Architecture News, 2010Co-Authors: Sebastian Banescu, Bogdan Pasca, Florent De Dinechin, Radu TudoranAbstract:The implementation of high-precision floating-point applications on reconfigurable hardware requires large Multipliers. Full Multipliers are the core of floating-point Multipliers. Truncated Multipliers, trading resources for a well-controlled accuracy degradation, are useful building blocks in situations where a full multiplier is not needed. This work studies the automated generation of such Multipliers using the embedded Multipliers and adders present in the DSP blocks of current FPGAs. The optimization of such Multipliers is expressed as a tiling problem, where a tile represents a hardware multiplier, and super-tiles represent combinations of several hardware Multipliers and adders, making efficient use of the DSP internal resources. This tiling technique is shown to adapt to full or truncated Multipliers. It addresses arbitrary precisions including single, double but also the quadruple precision introduced by the IEEE-754-2008 standard and currently unsupported by processor hardware. An open-source implementation is provided in the FloPoCo project.
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Multipliers for Floating-Point Double Precision and Beyond on FPGAs
2010Co-Authors: Sebastian Banescu, Bogdan Pasca, Florent De Dinechin, Radu TudoranAbstract:The implementation of high-precision floating-point applications on reconfigurable hardware requires a variety of large Multipliers: Standard Multipliers are the core of floating-point Multipliers; Truncated Multipliers, trading resources for a well-controlled accuracy degradation, are useful building blocks in situations where a full multiplier is not needed. This work studies the automated generation of such Multipliers using the embedded Multipliers and adders present in DSP blocks of current FPGAs. The optimization of such Multipliers is expressed as a tiling problem where a tile represents a hardware multiplier and super-tiles are the wiring of several hardware Multipliers making efficient use of the DSP internal resources. This tiling technique is shown to adapt to full or truncated Multipliers. It addresses arbitrary precisions including single, double but also in the quadruple precision introduced by the IEEE-754-2008 standard and currently unsupported by processor hardware. An open-source implementation is provided in the FloPoCo project.
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Large Multipliers with fewer DSP blocks
FPL 09: 19th International Conference on Field Programmable Logic and Applications, 2009Co-Authors: Florent De Dinechin, Bogdan PascaAbstract:Recent computing-oriented FPGAs feature DSP blocks including small embedded Multipliers. A large integer multiplier, for instance for a double-precision floating-point multiplier, consumes many of these DSP blocks. This article studies three non-standard implementation techniques of large Multipliers: the Karatsuba-Ofman algorithm, non-standard multiplier tiling, and specialized squarers. They allow for large Multipliers working at the peak frequency of the DSP blocks while reducing the DSP block usage. Their overhead in term of logic resources, if any, is much lower than that of emulating embedded Multipliers. Their latency overhead, if any, is very small. Complete algorithmic descriptions are provided, carefully mapped on recent Xilinx and Altera devices, and validated by synthesis results.
