The Experts below are selected from a list of 12591 Experts worldwide ranked by ideXlab platform
Athasit Surarerks - One of the best experts on this subject based on the ideXlab platform.
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on the fly conversion from signed digit number system into Complement Representation
2006Co-Authors: Veerasit Charoensiri, Athasit SurarerksAbstract:This paper proposes a generic algorithm for converting the redundant number Representation into the Complement number Representation using "on-the-fly" architecture, which can be taken place in parallel. This method can solve the carry propagation problem occurring in the conventional conversions, which are sequential algorithms. The detail in this paper shows that the conversion is computable by the "on-the-fly" technique and lead to a faster computation time. Moreover, the proposed methodology can perform the conversion of a number in any integer radix into the Complement Representation. The mathematical proofs of the proposed algorithm in terms of correctness are also included in this paper.
A N Willson - One of the best experts on this subject based on the ideXlab platform.
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the use of reduced two s Complement Representation in low power dsp design
2002Co-Authors: Kamran Azadet, A N WillsonAbstract:Two's Complement signal Representation is widely used in the implementation of arithmetic operations. However, it is well-known that its sign-extension can cause undesirable signal transitions in the MSBs of a data-path circuit. We propose a novel technique to reduce the signal transitions due to sign-extension while retaining the simplicity of the two's Complement arithmetic operations. The key idea is to generate a signal Representation dynamically according to the signal magnitude. This paper discusses the implementation techniques of using reduced Representation in data-path designs. We have applied our proposed techniques in several design examples and our experimental results have shown 13% to 32% power reductions.
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a low power adaptive filter using dynamic reduced 2 s Complement Representation
2002Co-Authors: Kamran Azadet, A N WillsonAbstract:We describe the IC implementation and testing of a low-power adaptive FIR filter. A new technique is used in its implementation, one that can be employed in other digital signal processing applications where input signals have large dynamic ranges. We propose the use of a reduced 2's Complement signal Representation to conditionally disable the internal signal transitions in the most-significant-bits of a data path. The key idea is to generate the signal Representation dynamically according to the signal magnitude. The proposed technique retains all of the easy-to-implement properties of the widely-used 2's Complement number Representation and is particularly suitable for the implementation of arithmetic operations. Over a 32% power savings has been achieved in our adaptive filter application.
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biased two s Complement Representation for low power dsp systems
1999Co-Authors: Keiyong Khoo, Chaoliang Chen, A N WillsonAbstract:This paper shows that the switching activity of the sign-extended bits in a two's Complement number in a DSP system can be reduced by the application of a bias to the system's input. The technique is easy to implement and requires only one to two additional adders. Experimental results show a 20% and 5% reduction in bit-switching activities for a typical voice grade signal and an FIR filter processing the signal, respectively.
Veerasit Charoensiri - One of the best experts on this subject based on the ideXlab platform.
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on the fly conversion from signed digit number system into Complement Representation
2006Co-Authors: Veerasit Charoensiri, Athasit SurarerksAbstract:This paper proposes a generic algorithm for converting the redundant number Representation into the Complement number Representation using "on-the-fly" architecture, which can be taken place in parallel. This method can solve the carry propagation problem occurring in the conventional conversions, which are sequential algorithms. The detail in this paper shows that the conversion is computable by the "on-the-fly" technique and lead to a faster computation time. Moreover, the proposed methodology can perform the conversion of a number in any integer radix into the Complement Representation. The mathematical proofs of the proposed algorithm in terms of correctness are also included in this paper.
Uguen Yohann - One of the best experts on this subject based on the ideXlab platform.
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Synthèse de haut niveau et optimisations arithmétiques
2019Co-Authors: Uguen YohannAbstract:High-level synthesis (HLS) tools offer increased productivity regarding FPGA programming. However, due to their relatively young nature, they still lack many arithmetic optimizations. This thesis proposes safe arithmetic optimizations that should always be applied. These optimizations are simple operator specializations, following the C semantic. Other require to a lift the semantic embedded in high-level input program languages, which are inherited from software programming, for an improved accuracy/cost/performance ratio. To demonstrate this claim, the sum-of-product of floating-point numbers is used as a case study. The sum is performed on a fixed-point format, which is tailored to the application, according to the context in which the operator is instantiated. In some cases, there is not enough information about the input data to tailor the fixed-point accumulator. The fall-back strategy used in this thesis is to generate an accumulator covering the entire floating-point range. This thesis explores different strategies for implementing such a large accumulator, including new ones. The use of a 2's Complement Representation instead of a sign+magnitude is demonstrated to save resources and to reduce the accumulation loop delay. Based on a tapered precision scheme and an exact accumulator, the posit number systems claims to be a candidate to replace the IEEE floating-point format. A throughout analysis of posit operators is performed, using the same level of hardware optimization as state-of-the-art floating-point operators. Their cost remains much higher that their floating-point counterparts in terms of resource usage and performance. Finally, this thesis presents a compatibility layer for HLS tools that allows one code to be deployed on multiple tools. This library implements a strongly typed custom size integer type along side a set of optimized custom operators.À cause de la nature relativement jeune des outils de synthèse de haut-niveau (HLS), de nombreuses optimisations arithmétiques n'y sont pas encore implémentées. Cette thèse propose des optimisations arithmétiques se servant du contexte spécifique dans lequel les opérateurs sont instanciés. Certaines optimisations sont de simples spécialisations d'opérateurs, respectant la sémantique du C. D'autres nécessitent de s'éloigner de cette sémantique pour améliorer le compromis précision/coût/performance. Cette proposition est démontrée sur des sommes de produits de nombres flottants. La somme est réalisée dans un format en virgule-fixe défini par son contexte. Quand trop peu d’informations sont disponibles pour définir ce format en virgule-fixe, une stratégie est de générer un accumulateur couvrant l'intégralité du format flottant. Cette thèse explore plusieurs implémentations d'un tel accumulateur. L'utilisation d'une représentation en complément à deux permet de réduire le chemin critique de la boucle d'accumulation, ainsi que la quantité de ressources utilisées. Un format alternatif aux nombres flottants, appelé posit, propose d'utiliser un encodage à précision variable. De plus, ce format est augmenté par un accumulateur exact. Pour évaluer précisément le coût matériel de ce format, cette thèse présente des architectures d'opérateurs posits, implémentés avec le même degré d'optimisation que celui de l'état de l'art des opérateurs flottants. Une analyse détaillée montre que le coût des opérateurs posits est malgré tout bien plus élevé que celui de leurs équivalents flottants. Enfin, cette thèse présente une couche de compatibilité entre outils de HLS, permettant de viser plusieurs outils avec un seul code. Cette bibliothèque implémente un type d'entiers de taille variable, avec de plus une sémantique strictement typée, ainsi qu'un ensemble d'opérateurs ad-hoc optimisés
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Optimisations arithmétiques et synthèse de haut niveau
2019Co-Authors: Uguen YohannAbstract:High-level synthesis (HLS) tools offer increased productivity regarding FPGA programming.However, due to their relatively young nature, they still lack many arithmetic optimizations.This thesis proposes safe arithmetic optimizations that should always be applied.These optimizations are simple operator specializations, following the C semantic.Other require to a lift the semantic embedded in high-level input program languages, which are inherited from software programming, for an improved accuracy/cost/performance ratio.To demonstrate this claim, the sum-of-product of floating-point numbers is used as a case study. The sum is performed on a fixed-point format, which is tailored to the application, according to the context in which the operator is instantiated.In some cases, there is not enough information about the input data to tailor the fixed-point accumulator.The fall-back strategy used in this thesis is to generate an accumulator covering the entire floating-point range.This thesis explores different strategies for implementing such a large accumulator, including new ones.The use of a 2's Complement Representation instead of a sign+magnitude is demonstrated to save resources and to reduce the accumulation loop delay.Based on a tapered precision scheme and an exact accumulator, the posit number systems claims to be a candidate to replace the IEEE floating-point format.A throughout analysis of posit operators is performed, using the same level of hardware optimization as state-of-the-art floating-point operators.Their cost remains much higher that their floating-point counterparts in terms of resource usage and performance. Finally, this thesis presents a compatibility layer for HLS tools that allows one code to be deployed on multiple tools.This library implements a strongly typed custom size integer type along side a set of optimized custom operators.À cause de la nature relativement jeune des outils de synthèse de haut-niveau (HLS), de nombreuses optimisations arithmétiques n'y sont pas encore implémentées. Cette thèse propose des optimisations arithmétiques se servant du contexte spécifique dans lequel les opérateurs sont instanciés.Certaines optimisations sont de simples spécialisations d'opérateurs, respectant la sémantique du C.D'autres nécéssitent de s'éloigner de cette sémantique pour améliorer le compromis précision/coût/performance.Cette proposition est démontré sur des sommes de produits de nombres flottants.La somme est réalisée dans un format en virgule-fixe défini par son contexte.Quand trop peu d’informations sont disponibles pour définir ce format en virgule-fixe, une stratégie est de générer un accumulateur couvrant l'intégralité du format flottant.Cette thèse explore plusieurs implémentations d'un tel accumulateur.L'utilisation d'une représentation en complément à deux permet de réduire le chemin critique de la boucle d'accumulation, ainsi que la quantité de ressources utilisées. Un format alternatif aux nombres flottants, appelé posit, propose d'utiliser un encodage à précision variable.De plus, ce format est augmenté par un accumulateur exact.Pour évaluer précisément le coût matériel de ce format, cette thèse présente des architectures d'opérateurs posits, implémentés avec le même degré d'optimisation que celui de l'état de l'art des opérateurs flottants.Une analyse détaillée montre que le coût des opérateurs posits est malgré tout bien plus élevé que celui de leurs équivalents flottants.Enfin, cette thèse présente une couche de compatibilité entre outils de HLS, permettant de viser plusieurs outils avec un seul code. Cette bibliothèque implémente un type d'entiers de taille variable, avec de plus une sémantique strictement typée, ainsi qu'un ensemble d'opérateurs ad-hoc optimisés
Feng Qian - One of the best experts on this subject based on the ideXlab platform.
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generalized look ahead number conversion from signed digit to Complement Representation with optical logic operations
2001Co-Authors: Feng QianAbstract:In this paper a generalized look-ahead logic algorithm for number conversion from signed-digit to its Complement Representation is developed. By properly encoding the signed digits, all the operations are performed by binary logic, and unified logical expressions can be obtained for conversion from modified-signed-digit (MSD) to 2's Complement, trinary signed-digit (TSD) to 3's Complement, and quaternary signed-digit (QSD) to 4's Complement. For optical implementation, a parallel logical array module using electron-trapping device is employed, which is suitable for realizing complex logic functions in the form of sum-of-product. The proposed algorithm and architecture are compatible with a general-purpose optoelectronic computing system.© (2001) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.
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code conversion from signed digit to Complement Representation based on look ahead optical logic operations
2001Co-Authors: Feng QianAbstract:We present, for the first time to our knowledge, a generalized lookahead logic algorithm for number conversion from signed-digit to Complement Representation. By properly encoding the signed-digits, all the operations are performed by binary logic, and unified logical expressions can be obtained for conversion from modified-signed-digit (MSD) to 2's Complement, trinary signed-digit (TSD) to 3's Complement, and quarternary signed-digit (QSD) to 4's Complement. For optical implementation, a parallel logical array module using an electron-trapping device is employed and experimental results are shown. This optical module is suitable for implementing complex logic functions in the form of the sum of the product. The algorithm and architecture are compatible with a general-purpose optoelectronic computing system. (C) 2001 Society of Photo-Optical Instrumentation Engineers.
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optical look ahead mode conversion from modified signed digit to 2 s Complement Representation
1999Co-Authors: Feng Qian, Hao Ruan, Liren LiuAbstract:The modified signed-digit (MSD) number system offers parallel arithmetic operations because of its redundancy property. For exploiting the high parallelism of the MSD Representation, MSD form and 2's Complement binary form have to be converted to and from each other. In this paper, an efficient lookahead-mode conversion algorithm is introduced. The operation can be performed in parallel by binary logic and is thus suitable for optical implementation. The optical system utilizing a single electronic trapping device is suggested to realize the required operations. By programming the illumination of data arrays, any complex logic operations of multiple variables can be performed easily. The main hardware can be stacked to construct a compact optoelectronic processor of versatile functions. A proof-of- the-principle experiment is demonstrated.