The Experts below are selected from a list of 18519 Experts worldwide ranked by ideXlab platform
Keshab K Parhi - One of the best experts on this subject based on the ideXlab platform.
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low cost parallel FIR Filter structures with 2 stage parallelism
IEEE Transactions on Circuits and Systems I-regular Papers, 2007Co-Authors: Chao Cheng, Keshab K ParhiAbstract:Based on recently published low-complexity parallel finite-impulse response (FIR) Filter structures, this paper proposes a new parallel FIR Filter structure with less hardware complexity. The subFilters in the previous parallel FIR structures are replaced by a second stage parallel FIR Filter. The proposed 2-stage parallel FIR Filter structures can efficiently reduce the number of required multiplications and additions at the expense of delay elements. For a 32-parallel 1152-tap FIR Filter, the proposed structure can save 5184 multiplications (67%), 2612 additions (30%), compared to previous parallel FIR structures, at the expense of 10089 delay elements (-133%). The proposed structures will lead to significant hardware savings because the hardware cost of a delay element is only a small portion of that of a multiplier, not including the savings in the number of additions
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hardware efficient fast parallel FIR Filter structures based on iterated short convolution
IEEE Transactions on Circuits and Systems, 2004Co-Authors: Chao Cheng, Keshab K ParhiAbstract:This paper presents an iterated short convolution (ISC) algorithm, based on the mixed radix algorithm and fast convolution algorithm. This ISC-based linear convolution structure is transposed to obtain a new hardware efficient fast parallel finite-impulse response (FIR) Filter structure, which saves a large amount of hardware cost, especially when the length of the FIR Filter is large. For example, for a 576-tap Filter, the proposed structure saves 17% to 42% of the multiplications, 17% to 44% of the delay elements, and 3% to 27% of the additions, of those of prior fast parallel structures, when the level of parallelism varies from 6 to 72. Their regular structures also facilitate automatic hardware implementation of parallel FIR Filters.
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hardware efficient fast parallel FIR Filter structures based on iterated short convolution
International Symposium on Circuits and Systems, 2004Co-Authors: Chao Cheng, Keshab K ParhiAbstract:This paper presents an iterated short convolution (ISC) algorithm, based on the mixed radix algorithm and fast convolution algorithm. This ISC based linear convolution structure is transposed to obtain a new hardware efficient fast parallel FIR Filter structure, which save a lot of amount of hardware cost, especially when the length of the FIR Filter is large. For example, for a 576-tap Filter, the proposed structure saves 16.7% to 43.6% of the delay elements and 2.9% to 27% of the additions, which prior fast parallel structures use, when the level of parallelism varies from 6 to 72. These proposed structures exhibit regular structure.
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frequency spectrum based low area low power parallel FIR Filter design
EURASIP Journal on Advances in Signal Processing, 2002Co-Authors: Jingyun Chung, Keshab K ParhiAbstract:Parallel (or block) FIR digital Filters can be used either for high-speed or low-power (with reduced supply voltage) applications. Traditional parallel Filter implementations cause linear increase in the hardware cost with respect to the block size. Recently, an efficient parallel FIR Filter implementation technique requiring a less-than linear increase in the hardware cost was proposed. This paper makes two contributions. FIRst, the Filter spectrum characteristics are exploited to select the best fast Filter structures. Second, a novel block Filter quantization algorithm is introduced. Using Filter benchmarks, it is shown that the use of the appropriate fast FIR Filter structures and the proposed quantization scheme can result in reduction in the number of binary adders up to 20%.
Chao Cheng - One of the best experts on this subject based on the ideXlab platform.
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low cost parallel FIR Filter structures with 2 stage parallelism
IEEE Transactions on Circuits and Systems I-regular Papers, 2007Co-Authors: Chao Cheng, Keshab K ParhiAbstract:Based on recently published low-complexity parallel finite-impulse response (FIR) Filter structures, this paper proposes a new parallel FIR Filter structure with less hardware complexity. The subFilters in the previous parallel FIR structures are replaced by a second stage parallel FIR Filter. The proposed 2-stage parallel FIR Filter structures can efficiently reduce the number of required multiplications and additions at the expense of delay elements. For a 32-parallel 1152-tap FIR Filter, the proposed structure can save 5184 multiplications (67%), 2612 additions (30%), compared to previous parallel FIR structures, at the expense of 10089 delay elements (-133%). The proposed structures will lead to significant hardware savings because the hardware cost of a delay element is only a small portion of that of a multiplier, not including the savings in the number of additions
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hardware efficient fast parallel FIR Filter structures based on iterated short convolution
IEEE Transactions on Circuits and Systems, 2004Co-Authors: Chao Cheng, Keshab K ParhiAbstract:This paper presents an iterated short convolution (ISC) algorithm, based on the mixed radix algorithm and fast convolution algorithm. This ISC-based linear convolution structure is transposed to obtain a new hardware efficient fast parallel finite-impulse response (FIR) Filter structure, which saves a large amount of hardware cost, especially when the length of the FIR Filter is large. For example, for a 576-tap Filter, the proposed structure saves 17% to 42% of the multiplications, 17% to 44% of the delay elements, and 3% to 27% of the additions, of those of prior fast parallel structures, when the level of parallelism varies from 6 to 72. Their regular structures also facilitate automatic hardware implementation of parallel FIR Filters.
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hardware efficient fast parallel FIR Filter structures based on iterated short convolution
International Symposium on Circuits and Systems, 2004Co-Authors: Chao Cheng, Keshab K ParhiAbstract:This paper presents an iterated short convolution (ISC) algorithm, based on the mixed radix algorithm and fast convolution algorithm. This ISC based linear convolution structure is transposed to obtain a new hardware efficient fast parallel FIR Filter structure, which save a lot of amount of hardware cost, especially when the length of the FIR Filter is large. For example, for a 576-tap Filter, the proposed structure saves 16.7% to 43.6% of the delay elements and 2.9% to 27% of the additions, which prior fast parallel structures use, when the level of parallelism varies from 6 to 72. These proposed structures exhibit regular structure.
Kaushik Roy - One of the best experts on this subject based on the ideXlab platform.
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computation sharing programmable FIR Filter for low power and high performance applications
IEEE Journal of Solid-state Circuits, 2004Co-Authors: Jongsun Park, Woopyo Jeong, H Mahmoodimeimand, Yongtao Wang, Hunsoo Choo, Kaushik RoyAbstract:This paper presents a programmable digital finite-impulse response (FIR) Filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR Filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR Filter was implemented and fabricated in CMOS 0.25-/spl mu/m technology based on the proposed architectural and circuit-level techniques. The chip's core contains approximately 130 K transistors and occupies 9.93 mm/sup 2/ area.
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high performance FIR Filter design based on sharing multiplication
IEEE Transactions on Very Large Scale Integration Systems, 2003Co-Authors: Jongsun Park, Khurram Muhammad, Kaushik RoyAbstract:Finite impulse response (FIR) Filtering can be expressed as multiplications of vectors by scalars. We present high-speed designs for FIR Filters based on a computation sharing multiplier which specifically targets computation re-use in vector-scalar products. The performance of the proposed implementation is compared with implementations based on carry-save and Wallace tree multipliers in 0.35-/spl mu/m technology. We show that sharing multiplier scheme improves speed by approximately 52 and 33% with respect to the FIR Filter implementations based on the carry-save multiplier and Wallace tree multiplier, respectively. In addition, sharing multiplier scheme has a relatively small power delay product than other multiplier schemes. Using voltage scaling, power consumption of the FIR Filter based on computation sharing multiplier can be reduced to 41% of the FIR Filter based on the Wallace tree multiplier for the same frequency of operation.
Jongsun Park - One of the best experts on this subject based on the ideXlab platform.
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a reconfigurable FIR Filter architecture to trade off Filter performance for dynamic power consumption
IEEE Transactions on Very Large Scale Integration Systems, 2011Co-Authors: Seokjae Lee, Jiwoong Choi, Seon Wook Kim, Jongsun ParkAbstract:This paper presents an architectural approach to the design of low power reconfigurable finite impulse response (FIR) Filter. The approach is well suited when the Filter order is fixed and not changed for particular applications, and efficient trade-off between power savings and Filter performance can be made using the proposed architecture. Generally, FIR Filter has large amplitude variations in input data and coefficients. Considering the amplitude of both the Filter coefficients and inputs, the proposed FIR Filter dynamically changes the Filter order. Mathematical analysis on power savings and Filter performance degradation and its experimental results show that the proposed approach achieves significant power savings without seriously compromising the Filter performance. The power savings is up to 41.9% with minor performance degradation, and the area overhead of the proposed scheme is less than 5.3% compared to the conventional approach.
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computation sharing programmable FIR Filter for low power and high performance applications
IEEE Journal of Solid-state Circuits, 2004Co-Authors: Jongsun Park, Woopyo Jeong, H Mahmoodimeimand, Yongtao Wang, Hunsoo Choo, Kaushik RoyAbstract:This paper presents a programmable digital finite-impulse response (FIR) Filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR Filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR Filter was implemented and fabricated in CMOS 0.25-/spl mu/m technology based on the proposed architectural and circuit-level techniques. The chip's core contains approximately 130 K transistors and occupies 9.93 mm/sup 2/ area.
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high performance FIR Filter design based on sharing multiplication
IEEE Transactions on Very Large Scale Integration Systems, 2003Co-Authors: Jongsun Park, Khurram Muhammad, Kaushik RoyAbstract:Finite impulse response (FIR) Filtering can be expressed as multiplications of vectors by scalars. We present high-speed designs for FIR Filters based on a computation sharing multiplier which specifically targets computation re-use in vector-scalar products. The performance of the proposed implementation is compared with implementations based on carry-save and Wallace tree multipliers in 0.35-/spl mu/m technology. We show that sharing multiplier scheme improves speed by approximately 52 and 33% with respect to the FIR Filter implementations based on the carry-save multiplier and Wallace tree multiplier, respectively. In addition, sharing multiplier scheme has a relatively small power delay product than other multiplier schemes. Using voltage scaling, power consumption of the FIR Filter based on computation sharing multiplier can be reduced to 41% of the FIR Filter based on the Wallace tree multiplier for the same frequency of operation.
Hunsoo Choo - One of the best experts on this subject based on the ideXlab platform.
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computation sharing programmable FIR Filter for low power and high performance applications
IEEE Journal of Solid-state Circuits, 2004Co-Authors: Jongsun Park, Woopyo Jeong, H Mahmoodimeimand, Yongtao Wang, Hunsoo Choo, Kaushik RoyAbstract:This paper presents a programmable digital finite-impulse response (FIR) Filter for high-performance and low-power applications. The architecture is based on a computation sharing multiplier (CSHM) which specifically targets computation re-use in vector-scalar products and can be effectively used in the low-complexity programmable FIR Filter design. Efficient circuit-level techniques, namely a new carry-select adder and conditional capture flip-flop (CCFF), are also used to further improve power and performance. A 10-tap programmable FIR Filter was implemented and fabricated in CMOS 0.25-/spl mu/m technology based on the proposed architectural and circuit-level techniques. The chip's core contains approximately 130 K transistors and occupies 9.93 mm/sup 2/ area.
