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Behrooz Parhami - One of the best experts on this subject based on the ideXlab platform.

  • adapting Computer Arithmetic structures to sustainable supercomputing in low power majority logic nanotechnologies
    IEEE Transactions on Sustainable Computing, 2018
    Co-Authors: Ghassem Jaberipur, Behrooz Parhami, Dariush Abedi
    Abstract:

    Petascale superComputers are already pushing power boundaries that can be supplied or dissipated cost-effectively; greater challenges await us in the era of exascale machines. We are thus motivated to study methods of reducing the energy cost of Arithmetic operations, which can be substantial in numerically intensive applications. Additionally, being both a widely-used operation in itself and an important building block for synthesizing other Arithmetic operations, has received much attention in this regard. Circuit and energy costs of fast adders are dominated by their fast carry networks. The availability of simple and energy-efficient majority function in certain emerging nanotechnologies (such as quantum-dot cellular automata, single-electron tunneling, tunneling phase logic, magnetic tunnel junction, nanoscale bar magnets, and memristors) has motivated our work to reformulate the carry recurrence in terms of fully-utilized majority elements, with all three inputs usefully employed. We compare our novel designs and resulting circuits to prior proposals based on 3-input majority elements in quantum-dot cellular automata, demonstrating advantages in both speed and circuit complexity. We also show that the performance and cost advantages carry over to at least one other emerging, energy-efficient technology, single-electron tunneling, raising hopes for achieving similar benefits with other technologies, which we review very briefly.

  • parallelism in Computer Arithmetic a historical perspective invited paper
    International Midwest Symposium on Circuits and Systems, 2018
    Co-Authors: Behrooz Parhami
    Abstract:

    Many early parallel processing breakthroughs emerged from the quest for faster and higher-throughput Arithmetic operations. Additionally, the influence of Arithmetic techniques on parallel Computer performance can be seen in diverse areas such the bit-serial Arithmetic units of early massively parallel SIMD Computers, pipelining and pipeline-chaining in vector machines, design of floating-point standards to ensure the accuracy and portability of numerically-intensive programs, and prominence of GPUs in today’s top-of-the-line superComputers. This paper contains a few representative samples of the many interactions and cross-fertilizations between Computer-Arithmetic and parallel-computation communities by presenting historical perspectives, case studies of state of art and practice, and directions for further collaboration.

  • Design and Evaluation of Decimal Array Multipliers
    2012
    Co-Authors: Saeid Gorgin, Ghassem Jaberipur, Behrooz Parhami
    Abstract:

    Hardware support for decimal Arithmetic has become an important focal point, both in the research arena and in commercial processor developments. Like their binary counterparts, decimal multipliers can be designed in a variety of ways, offering area and speed trade-offs. Pipelined array multipliers support high throughput, making them attractive in multiply-intensive applications. We propose two different architectures for decimal array multipliers based on (1) precomputed multiples and (2) decimal digit-multipliers. We compare the VLSI area and delay parameters of the resulting array multiplier designs with each other and with those of binary array multipliers covering the same range of inputs. Keywords––Array multiplier, Binary-coded decimal; Computer Arithmetic; Decimal calculation; Pipelining. Pipelining of Computer Arithmetic circuits is a longstanding practice for achieving high throughput. In this regard, array multipliers are not only particularly suitable for pipelined computations, but they also lead to enhanced circuit regularity. This regularity, when combined with shorter interconnects, translates to greatly improved performance [13]. In this paper, we offer two decimal array multiplier designs for conventional binary-coded-decimal (BCD) operands: one is based on selecting the partial products from among precomputed “easy ” multiples of the multiplicand [14], and the other on generating the partial products via BCD digit-multiplier cells [15]. Table I lists symbols and abbreviations used throughout this paper for easy reference. Table I Symbols and abbreviations used 1

  • Design and Evaluation of Decimal Array Multipliers
    2011
    Co-Authors: Saeid Gorgin, Ghassem Jaberipur, Behrooz Parhami
    Abstract:

    Hardware support for decimal Arithmetic has become an important focal point, both in the research arena and in commercial processor developments. Like their binary counterparts, decimal multipliers can be designed in a variety of ways, offering area and speed trade-offs. Pipelined array multipliers support high throughput, making them attractive in multiply-intensive applications. We propose two different architectures for decimal array multipliers based on (1) precomputed multiples and (2) decimal digit-multipliers. We compare the VLSI area and delay parameters of the resulting array multiplier designs with each other and with those of binary array multipliers covering the same range of inputs. Pipelining of Computer Arithmetic circuits is a longstanding practice for achieving high throughput. In this regard, array multipliers are not only particularly suitable for pipelined computations, but they also lead to enhanced circuit regularity. This regularity, when combined with shorter interconnects, translates to greatly improved performance [13]. In this paper, we offer two decimal array multiplier designs for conventional binary-coded-decimal (BCD) operands: one is based on selecting the partial products from among precomputed “easy ” multiples of the multiplicand [14], and the other on generating the partial products via BCD digit-multiplier cells [15]. Table I lists symbols and abbreviations used throughout this paper for easy reference. Keywords––Array multiplier, Binary-coded decimal; Computer Arithmetic; Decimal calculation; Pipelining. 1

  • Parity-preserving transformations in Computer Arithmetic
    Advanced Signal Processing Algorithms Architectures and Implementations XII, 2002
    Co-Authors: Behrooz Parhami
    Abstract:

    Parity checking comprises a low-redundancy method for the design of reliable digital systems. While quite effective for detecting single-bit transmission or storage errors, parity encoding has not been widely used for checking the correctness of Arithmetic results because parity is not preserved during Arithmetic operations and parity prediction requires fairly complex circuits in most cases. We propose a general strategy for designing parity-checked Arithmetic circuits that takes advantage of redundant intermediate representations. Because redundancy is often used for high performance anyway, the incremental cost of our proposed method is quite small. Unlike conventional binary numbers, redundant representations can be encoded and manipulated in such a way that parity is preserved in each step. Additionally, lack of carry propagation ensures that the effect of a fault is localized rather than catastrophic. After establishing the framework for our parity-preserving transformations in Computer Arithmetic, we illustrate some applications of the proposed strategy to the design of parity-checked adder/subtractors, multipliers, and other Arithmetic structures used in signal processing.

Peng Daiyuan - One of the best experts on this subject based on the ideXlab platform.

Ulrich Kulisch - One of the best experts on this subject based on the ideXlab platform.

  • Mathematics and Speed for Interval Arithmetic: A Complement to IEEE 1788
    ACM Transactions on Mathematical Software, 2019
    Co-Authors: Ulrich Kulisch
    Abstract:

    After a short introduction, the article begins with an axiomatic definition of rounded Arithmetic. The concepts of rounding and of rounded Arithmetic operations are defined in an axiomatic manner fully independent of special data formats and encodings. Basic properties of floating-point and interval Arithmetic can directly be derived from this abstract mathematical model. Interval operations are defined as set operations for elements of the set ¯IR of closed and connected sets of real numbers. As such, they form an algebraically closed subset of the powerset of the real numbers. This property leads to explicit formulas for the Arithmetic operations of floating-point intervals of ¯IF, which are executable on the Computer. Arithmetic for intervals of ¯IF forms an exception free calculus, i.e., Arithmetic operations for intervals of ¯IF always lead to intervals of ¯IF again. Later sections are concerned with programming support and hardware for interval Arithmetic. Both are a must and absolutely necessary to move interval Arithmetic more into the center of scientific computing. With some minor hardware additions, interval operations can be made as fast as simple floating-point operations. In vector and matrix spaces for real, complex, and interval data, the dot product is a fundamental Arithmetic operation. Computing the dot product of two vectors with floating-point components exactly substantially speeds up floating-point and interval Arithmetic as well as the accuracy of the computed result. Hardware needed for the exact dot product is very modest. The exact dot product is essential for long real and long interval Arithmetic. Section 9 illustrates that interval Arithmetic as developed in this article already has a long tradition. Products based on these ideas have been available since 1980. Implementing what the article advocates would have a profound effect on mathematical software. Modern processor architecture from Intel, for example, comes quite close to what is requested in this article.

  • up to date interval Arithmetic from closed intervals to connected sets of real numbers
    International Conference on Parallel Processing, 2016
    Co-Authors: Ulrich Kulisch
    Abstract:

    This paper unifies the representations of different kinds of Computer Arithmetic. It is motivated by the book The End of Error by John Gustafson [5]. Here interval Arithmetic just deals with connected sets of real numbers. These can be closed, open, half-open, bounded or unbounded.

  • complete interval Arithmetic and its implementation on the Computer
    Numerical Validation in Current Hardware Architectures, 2009
    Co-Authors: Ulrich Kulisch
    Abstract:

    Let $I\textit{I \kern-.55em R}$ be the set of closed and bounded intervals of real numbers. Arithmetic in $I\textit{I \kern-.55em R}$ can be defined via the power set $\textit{I \kern-.54em P}\textit{I \kern-.55em R}$ of real numbers. If divisors containing zero are excluded, Arithmetic in $I\textit{I \kern-.55em R}$ is an algebraically closed subset of the Arithmetic in $\textit{I \kern-.54em P}\textit{I \kern-.55em R}$, i.e., an operation in $I\textit{I \kern-.55em R}$ performed in $\textit{I \kern-.54em P}\textit{I \kern-.55em R}$ gives a result that is in $I\textit{I \kern-.55em R}$. Arithmetic in $\textit{I \kern-.54em P}\textit{I \kern-.55em R}$ also allows division by an interval that contains zero. Such division results in closed intervals of real numbers which, however, are no longer bounded. The union of the set $I\textit{I \kern-.55em R}$ with these new intervals is denoted by $(I\textit{I \kern-.55em R})$. This paper shows that Arithmetic operations can be extended to all elements of the set $(I\textit{I \kern-.55em R})$. Let $F \subset \textit{I \kern-.55em R}$ denote the set of floating-point numbers. On the Computer, Arithmetic in $(I\textit{I \kern-.55em R})$ is approximated by Arithmetic in the subset (IF ) of closed intervals with floating-point bounds. The usual exceptions of floating-point Arithmetic like underflow, overflow, division by zero, or invalid operation do not occur in (IF ).

  • Computer Arithmetic and validity theory implementation and applications
    2008
    Co-Authors: Ulrich Kulisch
    Abstract:

    The series is devoted to the publication of monographs and high-level textbooks in mathematics, mathematical methods and their applications. Apart from covering important areas of current interest, a major aim is to make topics of an interdisciplinary nature accessible to the non-specialist. The works in this series are addressed to advanced students and researchers in mathematics and theoretical physics. In addition, it can serve as a guide for lectures and seminars on a graduate level. The series de Gruyter Studies in Mathematics was founded ca. 35 years ago by the late Professor Heinz Bauer and Professor Peter Gabriel with the aim to establish a series of monographs and textbooks of high standard, written by scholars with an international reputation presenting current fields of research in pure and applied mathematics. While the editorial board of the Studies has changed with the years, the aspirations of the Studies are unchanged. In times of rapid growth of mathematical knowledge carefully written monographs and textbooks written by experts are needed more than ever, not least to pave the way for the next generation of mathematicians. In this sense the editorial board and the publisher of the Studies are devoted to continue the Studies as a service to the mathematical community. Please submit any book proposals to Niels Jacob. Titles in planning include Wolfgang Herfort, Karl H. Hofmann, and Francesco G. Russo, Periodic Locally Compact Groups: A Study of a Class of Totally Disconnected Topological Groups (2018) Mark M. Meerschaert, Alla Sikorskii, and Mohsen Zayernouri, Stochastic and Computational Models for Fractional Calculus, second edition (2018) Flavia Smarazzo and Alberto Tesei, Measure Theory: Radon Measures, Young Measures, and Applications to Parabolic Problems (2019) Elena Cordero and Luigi Rodino, Time-Frequency Analysis of Operators (2019) Kezheng Li, Group Schemes and Their Actions (2019; together with Tsinghua University Press) Mariusz Lemanczyk, Ergodic Theory: Spectral Theory, Joinings, and Their Applications (2020) Marco Abate, Holomorphic Dynamics on Hyperbolic Complex Manifolds (2021) Miroslava Antic, Joeri Van der Veken, and Luc Vrancken, Differential Geometry of Submanifolds: Submanifolds of Almost Complex Spaces and Almost Product Spaces (2021) Kai Liu, Ilpo Laine, and Lianzhong Yang, Complex Differential-Difference Equations (2021) Rajendra Vasant Gurjar, Kayo Masuda, and Masayoshi Miyanishi, Affine Space Fibrations (2022)

  • Advanced Arithmetic for the Digital Computer: Design of Arithmetic Units
    Electronic Notes in Theoretical Computer Science, 2000
    Co-Authors: Ulrich Kulisch
    Abstract:

    Abstract Advances in Computer technology are now so profound that the Arithmetic capability and repertoire of Computers can and should be expanded. Nowadays the elementary floating-point operations +, −, ×, / give computed results that coincide with the rounded exact result for any operands. Advanced Computer Arithmetic extends this accuracy requirement to all operations in the usual product spaces of computation: the real and complex vector spaces as well as their interval correspondents. This enhances the mathematical power of the digital Computer considerably. A new Computer operation, the scalar product, is fundamental to the development of advanced Computer Arithmetic. This paper studies the design of Arithmetic units for advanced Computer Arithmetic. Scalar product units are developed for different kinds of Computers like personal Computers, workstations, mainframes, super Computers or digital signal processors. The new expanded computational capability is gained at modest cost. The units put a methodology into modern Computer hardware which was available on old calculators before the electronic Computer entered the scene. In general the new Arithmetic units increase both the speed of computation as well as the accuracy of the computed result. The circuits developed in this paper show that there is no way to compute an approximation of a scalar product faster than the correct result. A collection of constructs in terms of which a source language may accommodate advanced Computer Arithmetic is described in the paper. The development of programming languages in the context of advanced Computer Arithmetic is reviewed. The simulation of the accurate scalar product on existing, conventional processors is discussed. Finally the theoretical foundation of advanced Computer Arithmetic is reviewed and a comparison with other approaches to achieving higher accuracy in computation is given. Shortcomings of existing processors and standards are discussed.

John L Hennessy - One of the best experts on this subject based on the ideXlab platform.

  • Computer organization and design the hardware software interface arm edition
    2016
    Co-Authors: David A Patterson, John L Hennessy
    Abstract:

    The new ARM Edition of Computer Organization and Design features a subset of the ARMv8-A architecture, which is used to present the fundamentals of hardware technologies, assembly language, Computer Arithmetic, pipelining, memory hierarchies, and I/O. With the post-PC era now upon us, Computer Organization and Design moves forward to explore this generational change with examples, exercises, and material highlighting the emergence of mobile computing and the Cloud. Updated content featuring tablet Computers, Cloud infrastructure, and the ARM (mobile computing devices) and x86 (cloud computing) architectures is included. An online companion Web site provides links to a free version of the DS-5 Community Edition (a free professional quality tool chain developed by ARM), as well as additional advanced content for further study, appendices, glossary, references, and recommended reading. Covers parallelism in depth with examples and content highlighting parallel hardware and software topicsFeatures the Intel Core i7, ARM Cortex-A53, and NVIDIA Fermi GPU as real-world examples throughout the bookAdds a new concrete example, "Going Faster," to demonstrate how understanding hardware can inspire software optimizations that improve performance by 200XDiscusses and highlights the "Eight Great Ideas" of Computer architecture: Performance via Parallelism; Performance via Pipelining; Performance via Prediction; Design for Moore's Law; Hierarchy of Memories; Abstraction to Simplify Design; Make the Common Case Fast; and Dependability via Redundancy. Includes a full set of updated exercises

  • Computer organization and design fifth edition the hardware software interface
    2013
    Co-Authors: David A Patterson, John L Hennessy
    Abstract:

    The 5th edition of Computer Organization and Design moves forward into the post-PC era with new examples, exercises, and material highlighting the emergence of mobile computing and the cloud. This generational change is emphasized and explored with updated content featuring tablet Computers, cloud infrastructure, and the ARM (mobile computing devices) and x86 (cloud computing) architectures. Because an understanding of modern hardware is essential to achieving good performance and energy efficiency, this edition adds a new concrete example, "Going Faster," used throughout the text to demonstrate extremely effective optimization techniques. Also new to this edition is discussion of the "Eight Great Ideas" of Computer architecture. As with previous editions, a MIPS processor is the core used to present the fundamentals of hardware technologies, assembly language, Computer Arithmetic, pipelining, memory hierarchies and I/O. Instructors looking for4th Edition teaching materials should e-mail textbook@elsevier.com. Includes new examples, exercises, and material highlighting the emergence of mobile computing and the Cloud. Covers parallelism in depth with examples and content highlighting parallel hardware and software topics Features the Intel Core i7, ARM Cortex-A8 and NVIDIA Fermi GPU as real-world examples throughout the book Adds a new concrete example, "Going Faster," to demonstrate how understanding hardware can inspire software optimizations that improve performance by 200 times. Discusses and highlights the "Eight Great Ideas" of Computer architecture: Performance via Parallelism; Performance via Pipelining; Performance via Prediction; Design for Moore's Law; Hierarchy of Memories; Abstraction to Simplify Design; Make the Common Case Fast; and Dependability via Redundancy. Includes a full set of updated and improved exercises.

  • Computer organization and design revised fourth edition fourth edition the hardware software interface
    2011
    Co-Authors: David A Patterson, John L Hennessy
    Abstract:

    This Fourth Revised Edition of Computer Organization and Design includes a complete set of updated and new exercises, along with improvements and changes suggested by instructors and students. Focusing on the revolutionary change taking place in industry today--the switch from uniprocessor to multicore microprocessors--this classic textbook has a modern and up-to-date focus on parallelism in all its forms. Examples highlighting multicore and GPU processor designs are supported with performance and benchmarking data. As with previous editions, a MIPS processor is the core used to present the fundamentals of hardware technologies, assembly language, Computer Arithmetic, pipelining, memory hierarchies and I/O. Sections on the ARM and x86 architectures are also included.The companion CD provides a toolkit of simulators and compilers along with tutorials for using them, as well as advanced content for further study and a search utility for finding content on the CD and in the printed text. For the convenience of readers who have purchased an ebook edition or who may have misplaced the CD-ROM, all CD content is available as a download at bit.ly/nFXcLqThis Revised Fourth Edition of Computer Organization and Design has been updated with new exercises and improvements throughout suggested by instructors teaching from the bookCovers the revolutionary change from sequential to parallel computing, with a chapter on parallelism and sections in every chapter highlighting parallel hardware and software topicsIncludes an appendix by the Chief Scientist and the Director of Architecture of NVIDIA covering the emergence and importance of the modern GPU, describing in detail for the first time the highly parallel, highly multithreaded multiprocessor optimized for visual computing

  • Computer organization and design the hardware software interface revised 4th edition ed 4
    2011
    Co-Authors: David A Patterson, John L Hennessy
    Abstract:

    This Fourth Revised Edition of Computer Organization and Design includes a complete set of updated and new exercises, along with improvements and changes suggested by instructors and students. Focusing on the revolutionary change taking place in industry today--the switch from uniprocessor to multicore microprocessors--this classic textbook has a modern and up-to-date focus on parallelism in all its forms. Examples highlighting multicore and GPU processor designs are supported with performance and benchmarking data. As with previous editions, a MIPS processor is the core used to present the fundamentals of hardware technologies, assembly language, Computer Arithmetic, pipelining, memory hierarchies and I/O. Sections on the ARM and x86 architectures are also included. The companion CD provides a toolkit of simulators and compilers along with tutorials for using them, as well as advanced content for further study and a search utility for finding content on the CD and in the printed text. For the convenience of readers who have purchased an ebook edition or who may have misplaced the CD-ROM, all CD content is available as a download at bit.ly/nFXcLq This Revised Fourth Edition of Computer Organization and Design has been updated with new exercises and improvements throughout suggested by instructors teaching from the book Covers the revolutionary change from sequential to parallel computing, with a chapter on parallelism and sections in every chapter highlighting parallel hardware and software topics Includes an appendix by the Chief Scientist and the Director of Architecture of NVIDIA covering the emergence and importance of the modern GPU, describing in detail for the first time the highly parallel, highly multithreaded multiprocessor optimized for visual computing

  • Computer organization and design fourth edition fourth edition the hardware software interface the morgan kaufmann series in Computer architecture and design
    2008
    Co-Authors: David A Patterson, John L Hennessy
    Abstract:

    The classic textbook for Computer systems analysis and design, Computer Organization and Design, has been thoroughly updated to provide a new focus on the revolutionary change taking place in industry today: the switch from uniprocessor to multicore microprocessors. This new emphasis on parallelism is supported by updates reflecting the newest technologies with examples highlighting the latest processor designs, benchmarking standards, languages and tools. As with previous editions, a MIPS processor is the core used to present the fundamentals of hardware technologies, assembly language, Computer Arithmetic, pipelining, memory hierarchies and I/O. Along with its increased coverage of parallelism, this new edition offers new content on Flash memory and virtual machines as well as a new and important appendix written by industry experts covering the emergence and importance of the modern GPU (graphics processing unit), the highly parallel, highly multithreaded multiprocessor optimized for visual computing.A new exercise paradigm allows instructors to reconfigure the 600 exercises included in the book to easily generate new exercises and solutions of their own. A CD provides a toolkit of simulators and compilers along with tutorials for using them as well as additional problems and solutions, and references.

Balasubramanian P - One of the best experts on this subject based on the ideXlab platform.

  • Approximate Early Output Asynchronous Adders Based on Dual-Rail Data Encoding and 4-Phase Return-to-Zero and Return-to-One Handshaking
    2018
    Co-Authors: Balasubramanian P
    Abstract:

    Approximate computing is emerging as an alternative to accurate computing due to its potential for realizing digital circuits and systems with low power dissipation, less critical path delay, and less area occupancy for an acceptable trade-off in the accuracy of results. In the domain of Computer Arithmetic, several approximate adders and multipliers have been designed and their potential have been showcased versus accurate adders and multipliers for practical digital signal processing applications. Nevertheless, in the existing literature, almost all the approximate adders and multipliers reported correspond to the synchronous design method. In this work, we consider robust asynchronous i.e. quasi-delay-insensitive realizations of approximate adders by employing delay-insensitive codes for data representation and processing, and the 4-phase handshake protocols for data communication. The 4-phase handshake protocols used are the return-to-zero and the return-to-one protocols. Specifically, we consider the implementations of 32-bit approximate adders based on the return-to-zero and return-to-one handshake protocols by adopting the delay-insensitive dual-rail code for data encoding. We consider a range of approximations varying from 4-bits to 20-bits for the least significant positions of the accurate 32-bit asynchronous adder. The asynchronous adders correspond to early output (i.e. early reset) type, which are based on the well-known ripple carry adder architecture. The experimental results show that approximate asynchronous adders achieve reductions in the design metrics such as latency, cycle time, average power dissipation, and silicon area compared to the accurate asynchronous adders. Further, the reductions in the design metrics are greater for the return-to-one protocol compared to the return-to-zero protocol. The design metrics were estimated using a 32/28nm CMOS technology.Comment: arXiv admin note: text overlap with arXiv:1711.0233

  • Approximate Ripple Carry and Carry Lookahead Adders - A Comparative Analysis
    2017
    Co-Authors: Balasubramanian P, Dang C, Maskell D L, Prasad K
    Abstract:

    Approximate ripple carry adders (RCAs) and carry lookahead adders (CLAs) are presented which are compared with accurate RCAs and CLAs for performing a 32-bit addition. The accurate and approximate RCAs and CLAs are implemented using a 32/28nm CMOS process. Approximations ranging from 4- to 20-bits are considered for the less significant adder bit positions. The simulation results show that approximate RCAs report reductions in the power-delay product (PDP) ranging from 19.5% to 82% than the accurate RCA for approximation sizes varying from 4- to 20-bits. Also, approximate CLAs report reductions in PDP ranging from 16.7% to 74.2% than the accurate CLA for approximation sizes varying from 4- to 20-bits. On average, for the approximation sizes considered, it is observed that approximate CLAs achieve a 46.5% reduction in PDP compared to the approximate RCAs. Hence, approximate CLAs are preferable over approximate RCAs for the low power implementation of approximate Computer Arithmetic

  • Design of Synchronous Section-Carry Based Carry Lookahead Adders with Improved Figure of Merit
    2017
    Co-Authors: Balasubramanian P
    Abstract:

    The section-carry based carry lookahead adder (SCBCLA) architecture was proposed as an efficient alternative to the conventional carry lookahead adder (CCLA) architecture for the physical implementation of Computer Arithmetic. In previous related works, self-timed SCBCLA architectures and synchronous SCBCLA architectures were realized using standard cells and FPGAs. In this work, we deal with improved realizations of synchronous SCBCLA architectures designed in a semi-custom fashion using standard cells. The improvement is quantified in terms of a figure of merit (FOM), where the FOM is defined as the inverse product of power, delay and area. Since power, delay and area of digital designs are desirable to be minimized, the FOM is desirable to be maximized. Starting from an efficient conventional carry lookahead generator, we show how an optimized section-carry based carry lookahead generator is realized. In comparison with our recent work dealing with standard cells based implementation of SCBCLAs to perform 32-bit addition of two binary operands, we show in this work that with improved section-carry based carry lookahead generators, the resulting SCBCLAs exhibit significant improvements in FOM. Compared to the earlier optimized hybrid SCBCLA, the proposed optimized hybrid SCBCLA improves the FOM by 88.3%. Even the optimized hybrid CCLA features improvement in FOM by 77.3% over the earlier optimized hybrid CCLA. However, the proposed optimized hybrid SCBCLA is still the winner and has a better FOM than the currently optimized hybrid CCLA by 15.3%. All the CCLAs and SCBCLAs are implemented to realize 32-bit dual-operand binary addition using a 32/28nm CMOS process.Comment: arXiv admin note: text overlap with arXiv:1603.0796