The Experts below are selected from a list of 438 Experts worldwide ranked by ideXlab platform

Rungbin Lin - One of the best experts on this subject based on the ideXlab platform.

  • Standard cell like viaconfigurable logic block for structured ASICs
    2015
    Co-Authors: Huihsiang Tung, Chienchung Lai, Rungbin Lin
    Abstract:

    A structured ASIC has some arrays of pre-fabricated yet configurable logic blocks (CLBs) with/without a regular routing fabric. In this paper, we propose a standard cell like via-configurable logic block (VCLB). We design a 0.18um standard cell library based on our VCLB and establish a design flow using as many commercial tools as possible. We also propose a method to evaluate the viability of a structured ASIC fabric. Our structured ASIC fabric with programmable metals for routing achieves a delay of 2.7 times, an area of 3 times, and a power of 1.5 times that attained by the designs using a commercial cell library. 1

  • logic block and design methodology for via configurable structured asic using dual supply voltages
    Great Lakes Symposium on VLSI, 2014
    Co-Authors: Takai Lin, Kuenwey Lin, Changhao Chiu, Rungbin Lin
    Abstract:

    This paper presents a via-configurable logic block and a design methodology for realizing fine-grained dual-supply-voltage structured ASIC. Experiments with a 90nm process technology show that, given various timing budgets, our approach can achieve up to 44% energy reduction with 1.6% area overhead on level converters. Compared with GECVS, our approach converts up to 39% more high-supply voltage gates into low-supply voltage gates.

  • via configurable logic block architectures for standard cell like structured asics
    Proceedings of the 2009 12th International Symposium on Integrated Circuits, 2009
    Co-Authors: Huihsiang Tung, Yuchen Chen, Dawei Hsu, Shihjung Hsu, Sinyu Chen, Rungbin Lin
    Abstract:

    In this paper, we investigate via-configurable logic block (VCLB) architectures of different granularities and logic styles for standard-cell like structured ASIC. VCLB granularity ranges from a few to tens of transistors. logic styles include those realized using series-parallel transistors and look-up table. VCLBs are designed to enable a standard cell design style so that we can establish a structured ASIC design flow using most of the existing tools. VCLBs are employed to construct cell libraries, each consisting of a few tens of cells to several hundred cells. This broad spectrum of VCLB architectures is evaluated in terms of delay, power, and area of designs.

  • standard cell like via configurable logic block for structured asics
    IEEE Computer Society Annual Symposium on VLSI, 2008
    Co-Authors: Huihsiang Tung, Chienchung Lai, Rungbin Lin
    Abstract:

    A structured ASIC has some arrays of pre-fabricated yet configurable logic blocks (CLBs) with/without a regular routing fabric. In this paper, we propose a standard cell like via-configurable logic block (VCLB). We design a 0.18 um standard cell library based on our VCLB and establish a design flow using as many commercial tools as possible. We also propose a method to evaluate the viability of a structured ASIC fabric. Our structured ASIC fabric with programmable metals for routing achieves a delay of 2.7 times, an area of 3 times, and a power of 1.5 times that attained by the designs using a commercial cell library.

Mohammed Niamat - One of the best experts on this subject based on the ideXlab platform.

  • design of a nanoscale quantum dot cellular automata configurable logic block for fpgas
    International Midwest Symposium on Circuits and Systems, 2012
    Co-Authors: Hemant Balijepalli, Mohammed Niamat
    Abstract:

    This paper presents a novel design of a configurable logic block (CLB) for a Field Programmable Gate Array (FPGA) based on a computing scheme in nanoscale technology called the Quantum-dot Cellular Automata (QCA). In QCA technology, the cells made of quantum dots transmit information from one cell to the other based on Coulombic repulsion between the electrons. The main goal behind the design of the CLB is to ultimately design a miniscule nano FPGA without transistors for the ‘beyond CMOS era’ of the 2020s. Unlike previous research in this area, the attempt here is to take advantage of the unique QCA features in building the architecture. It is found that the proposed CLB has less latency and occupies less number of cells as compared to earlier designs. Different components of the CLB including a (4×16) decoder, a D-latch, a multiplexer and an RS-flip flop are designed, and simulated using the QCADesigner tool for functional correctness.

  • qca design and implementation of sram based fpga configurable logic block
    International Midwest Symposium on Circuits and Systems, 2010
    Co-Authors: Mohammed Niamat, Sowmya Panuganti, Tejas Raviraj
    Abstract:

    This paper presents the design and simulation of a configurable logic block (CLB) using the Quantum-Dot Cellular Automata (QCA) technology. The modeling, implementation, and successful simulation of a CLB slice for a nano quantum FPGA are discussed. We have drawn comparisons with various FPGA architectures at the quantum level and optimized the proposed architecture with respect to area and latency. The design is modeled using standard QCA cells with multiple layers for reliable interconnect crossovers. The design of the CLB is implemented and simulated using the QCA Designer software tool.

V Kamakoti - One of the best experts on this subject based on the ideXlab platform.

  • Cluster-based Detection of SEU-caused Errors in LUTs of
    2014
    Co-Authors: Sram-based Fpgas, Vikram Chandrasekhar, M Sashikanth, V Kamakoti, E. Syam, Sundar Reddy, N. Vijaykrishnan
    Abstract:

    Abstract — This paper proposes a cluster-based parity-checking technique that can detect 100 % of all Single Event Up-set (SEU) faults in the LUTs of SRAM-based FPGAs. The pa-per describes two different configurable logic block (CLB) ar-chitectures that could be used to implement the proposed SEU detection technique. Of the two, the first architecture can per-form at-speed testing of the LUTs without interrupting the nor-mal functioning of the FPGA. The second one works by switching the CLBs from normal-mode to testing-mode and vice-versa. The LUTs are tested in the testing-mode. The switching frequency can be externally programmed and hence varied depending on the rate of SEU occurrences. Both the proposed architectures were compared with the Xilinx Virtex and Virtex Pro architec-ture. The proposed architectures require only (when compared with Virtex) and (when compared with Virtex Pro) additional SRAM configuration bits per LUT. This is extremely low when compared to the additional SRAM configuration bits required by CLB architectures used to implement standard DWC tech-niques for detecting SEUs in LUTs. The area requirements of both the proposed architectures are also significantly less than the area requirements of DWC techniques. The proposed detection technique requires only clock cycles of the Xilinx Virtex inter-nal clock to detect the effect of an SEU in any LUT of the FPGA. I

  • an area and configuration bit optimized clb architecture and timing driven packing for fpgas
    International Conference on VLSI Design, 2006
    Co-Authors: Vivek Garg, Vikram Chandrasekhar, M Sashikanth, V Kamakoti
    Abstract:

    This paper proposes a function-generation based area-aware configurable logic block (CLB) architecture and an associated packing technique, for SRAM-based FPGAs. The new CLB architecture provides the same logic functionality, but occupies 38% less area, consumes 38.31% less power and requires 50% less configuration-bits per CLB when compared to the standard 4-LUT CLB architecture. The proposed packing technique is timing-driven and is shown to produce designs with almost same routing cost and performance overhead as that produced by the T-VPack algorithm on standard benchmark circuits.

Huihsiang Tung - One of the best experts on this subject based on the ideXlab platform.

  • Standard cell like viaconfigurable logic block for structured ASICs
    2015
    Co-Authors: Huihsiang Tung, Chienchung Lai, Rungbin Lin
    Abstract:

    A structured ASIC has some arrays of pre-fabricated yet configurable logic blocks (CLBs) with/without a regular routing fabric. In this paper, we propose a standard cell like via-configurable logic block (VCLB). We design a 0.18um standard cell library based on our VCLB and establish a design flow using as many commercial tools as possible. We also propose a method to evaluate the viability of a structured ASIC fabric. Our structured ASIC fabric with programmable metals for routing achieves a delay of 2.7 times, an area of 3 times, and a power of 1.5 times that attained by the designs using a commercial cell library. 1

  • via configurable logic block architectures for standard cell like structured asics
    Proceedings of the 2009 12th International Symposium on Integrated Circuits, 2009
    Co-Authors: Huihsiang Tung, Yuchen Chen, Dawei Hsu, Shihjung Hsu, Sinyu Chen, Rungbin Lin
    Abstract:

    In this paper, we investigate via-configurable logic block (VCLB) architectures of different granularities and logic styles for standard-cell like structured ASIC. VCLB granularity ranges from a few to tens of transistors. logic styles include those realized using series-parallel transistors and look-up table. VCLBs are designed to enable a standard cell design style so that we can establish a structured ASIC design flow using most of the existing tools. VCLBs are employed to construct cell libraries, each consisting of a few tens of cells to several hundred cells. This broad spectrum of VCLB architectures is evaluated in terms of delay, power, and area of designs.

  • standard cell like via configurable logic block for structured asics
    IEEE Computer Society Annual Symposium on VLSI, 2008
    Co-Authors: Huihsiang Tung, Chienchung Lai, Rungbin Lin
    Abstract:

    A structured ASIC has some arrays of pre-fabricated yet configurable logic blocks (CLBs) with/without a regular routing fabric. In this paper, we propose a standard cell like via-configurable logic block (VCLB). We design a 0.18 um standard cell library based on our VCLB and establish a design flow using as many commercial tools as possible. We also propose a method to evaluate the viability of a structured ASIC fabric. Our structured ASIC fabric with programmable metals for routing achieves a delay of 2.7 times, an area of 3 times, and a power of 1.5 times that attained by the designs using a commercial cell library.

Scott C Smith - One of the best experts on this subject based on the ideXlab platform.

  • design and implementation of fpga configuration logic block using asynchronous static ncl
    IEEE Region 10 Conference, 2008
    Co-Authors: I P Dugganapally, Waleed K Alassadi, T Tammina, Scott C Smith
    Abstract:

    This paper proposes the design of a FPGA configurable logic block (CLB) using asynchronous static NULL convention logic (NCL) Library. The proposed design uses three static LUT's for implementing NCL logic functions. Each LUT can be configured to function as any one of the 27 fundamental NCL Static gates. The proposed CLB supports 10 inputs and three different outputs, each with resettable and inverting variations. The CLB has two modes: Configuration mode and operation mode. The static NCL FPGA CLB is simulated at the transistor level using the 1.8 V, 180 nm TSMC CMOS process.

  • design and implementation of fpga configuration logic block using asynchronous semi static ncl circuits
    IEEE Region 10 Conference, 2008
    Co-Authors: I P Dugganapally, Waleed K Alassadi, V Pillai, Scott C Smith
    Abstract:

    This paper proposes the design of a FPGA configurable logic block (CLB) using asynchronous semi-static NULL convention logic (NCL) Library. The proposed design uses three semi-static LLT's for implementing NCL logic functions. Each LLT can be configured to function as any one of the 27 fundamental NCL Semi-Static gates. The proposed CLB supports 10 inputs and three different outputs, each with resettable and inverting variations. The CLB has two modes: Configuration mode and Operation mode. The Static NCL FPGA CLB is simulated at the transistor level using the 1.8 V, 180 nm TSMC CMOS process.