The Experts below are selected from a list of 43767 Experts worldwide ranked by ideXlab platform

Joseph H Saleh - One of the best experts on this subject based on the ideXlab platform.

  • interdependent multi layer networks modeling and survivability analysis with applications to space based networks
    PLOS ONE, 2013
    Co-Authors: Jeanfrancois Castet, Joseph H Saleh
    Abstract:

    : This article develops a novel approach and algorithmic tools for the modeling and survivability analysis of networks with heterogeneous nodes, and examines their application to space-based networks. Space-based networks (SBNs) allow the sharing of spacecraft on-orbit resources, such as data storage, processing, and downlink. Each spacecraft in the network can have different subsystem composition and functionality, thus resulting in node heterogeneity. Most traditional survivability analyses of networks assume node homogeneity and as a result, are not suited for the analysis of SBNs. This work proposes that heterogeneous networks can be modeled as interdependent multi-layer networks, which enables their survivability analysis. The multi-layer aspect captures the breakdown of the network according to common functionalities across the different nodes, and it allows the emergence of homogeneous sub-networks, while the interdependency aspect constrains the network to capture the physical characteristics of each node. Definitions of primitives of failure propagation are devised. Formal characterization of interdependent multi-layer networks, as well as algorithmic tools for the analysis of failure propagation across the network are developed and illustrated with space applications. The SBN applications considered consist of several networked spacecraft that can tap into each other's Command and Data Handling subsystem, in case of failure of its own, including the Telemetry, Tracking and Command, the Control Processor, and the Data Handling sub-subsystems. Various design insights are derived and discussed, and the capability to perform trade-space analysis with the proposed approach for various network characteristics is indicated. The select results here shown quantify the incremental survivability gains (with respect to a particular class of threats) of the SBN over the traditional monolith spacecraft. Failure of the connectivity between nodes is also examined, and the results highlight the importance of the reliability of the wireless links between spacecraft (nodes) to enable any survivability improvements for space-based networks.

  • epidemiology of satellite anomalies and failures a subsystem centric approach
    Acta Astronautica, 2011
    Co-Authors: Rachel A Haga, Joseph H Saleh
    Abstract:

    Abstract Epidemiology is the basic science of public health and it investigates the distribution, frequency, rates, and drivers of health-related states and illnesses in specific populations. We adopt in this article some of Epidemiology's concepts and approaches, and instead of human population and diseases, we focus on a satellite population and its on-orbit anomalies and failures. We analyze an extensive database of geosynchronous satellite anomalies and failures (retrospective cohort study) and develop for each spacecraft subsystem a health scorecard synthesizing its track record of on-orbit failure events. We include results on the severity of the failure events in each subsystem's health scorecard (distribution and rates). We also provide for each subsystem its failure concentration ratio or the extent to which a single satellite in our population has experienced multiple failure events from the same subsystem. Next, having derived health scorecards for ten satellite subsystems identified in the database, we conduct a comparative analysis of the propensity and severity of failures between these subsystems. We identify for example several major subsystems driving on-orbit failure events, such as the Thruster/Fuel, the Solar Array, the Payload, and the Telemetry Tracking and Command (TTC) subsystems. In addition, we find that the Control Processor, the Mechanisms, and the Solar Array Deployment subsystems are sufficiently robust and contribute a minor share to the overall failure events on orbit. Furthermore, we find for example that while the attitude Control subsystem and the batteries exhibit roughly similar average failure rates, they have very different behaviors in terms of the severity of anomalies they experience: the former primarily failing “soft” (minor anomaly), whereas the latter, the batteries most often fail “hard” with major non-repairable degradations that affect operation of a satellite on a permanent basis. The results here provided should prove helpful to satellite manufacturers by allowing them to hone in on problematic subsystems that would benefit most from reliability improvements.

  • epidemiology of satellite anomalies and failures a subsystem centric approach
    IEEE Aerospace Conference, 2011
    Co-Authors: Rachel A Haga, Joseph H Saleh
    Abstract:

    Epidemiology is the basic science of public health and it investigates the distribution, frequency, rates, and drivers of health-related states and illnesses in specific populations. 12We adopt in this article some of Epidemiology's concepts and approaches, and instead of human population and diseases, we focus on a satellite population and its on-orbit anomalies and failures. A total of 168 satellites were analyzed in this work, and they have logged 968.5 years on orbit. We analyze an extensive database of geosynchronous satellite anomalies and failures (retrospective cohort study) and develop for each spacecraft subsystem a health scorecard synthesizing its track record of on-orbit failure events. We include results on the severity of the failure events in each subsystem's health scorecard (distribution and rates). We also provide for each subsystem its failure concentration ratio or the extent to which a single satellite in our population has experienced multiple failure events from the same subsystem. Next, having derived health scorecards for ten satellite subsystems identified in the database, we conduct a comparative analysis of the propensity and severity of failures between these subsystems. We identify for example several major subsystems driving on-orbit failure events, such as the Thruster/Fuel, the Solar Array, the Payload, and the Telemetry Tracking and Command (TTC) subsystems. In addition, we find that the Control Processor, the Mechanisms, and the Solar Array Deployment subsystems are sufficiently robust and contribute a minor share to the overall failure events on orbit. Furthermore, we find for example that while the attitude Control subsystem and the Batteries exhibit roughly similar average failure rates, they have very different behaviors in terms of the severity of anomalies they experience: the former primarily failing “soft” (minor anomaly), whereas the latter, the batteries most often fail “hard” with major non-repairable degradations that affect operation of a satellite on a permanent basis. The results here provided should prove helpful to satellite manufacturers by allowing them to hone in on problematic subsystems that would benefit most from reliability improvements.

Tamio Arai - One of the best experts on this subject based on the ideXlab platform.

  • an integrated memory array Processor for embedded image recognition systems
    IEEE Transactions on Computers, 2007
    Co-Authors: S Okazaki, Tamio Arai
    Abstract:

    Embedded Processors for video image recognition in most cases not only need to address the conventional cost (die size and power) versus real-time performance issue, but must also maintain high flexibility due to the immense diversity of recognition targets, situations, and applications. This paper describes IMAP, a highly parallel SIMD linear Processor and memory array architecture that addresses these trade-off requirements. By using parallel and systolic algorithmic techniques, but based on a simple linear array architecture, IMAP successfully exploits not only the straightforward per-image row data level parallelism (DLP), but also the inherent DLP of other memory access patterns frequently found in various image recognition tasks, while allowing programming to be done using an explicit parallel C language (1DC). We describe and evaluate IMAP-CE, one of the latest IMAP Processors, integrating 128 100 MHz 8 bit 4-way VLIW PEs, 128 2 KByte RAMs, and one 16 bit RISC Control Processor onto a single chip. The PE instruction set is enhanced to support 1DC code. The die size of IMAP-CE is 11 times11 mm2 integrating 32.7 M transistors, while the power consumption is, on average, approximately 2 watts. IMAP-CE is evaluated mainly by comparing its performance while running 1DC code with that of a 2.4 GHz Intel P4 running optimized C code. Based on the use of parallelizing techniques, benchmark results show a speed increase of up to 20 times for image filter kernels and of 4 times for a full image recognition application

  • an integrated memory array Processor architecture for embedded image recognition systems
    International Symposium on Computer Architecture, 2005
    Co-Authors: Shorin Kyo, Shinichiro Okazaki, Tamio Arai
    Abstract:

    Embedded Processors for video image recognition require to address both the cost (die size and power) versus real-time performance issue, and also to achieve high flexibility due to the immense diversity of recognition targets, situations, and applications. This paper describes IMAP, a highly parallel SIMD linear Processor and memory array architecture that addresses these trading-off requirements. By using parallel and systolic algorithmic techniques, despite of its simple architecture IMAP achieves to exploit not only the straightforward per image row data level parallelism (DLP), but also the inherent DLP of other memory access patterns frequently found in various image recognition tasks, under the use of an explicit parallel C language (1DC). We describe and evaluate IMAP-CE, a latest IMAP Processor, which integrates 128 of 100MHz 8 bit4-way VLIW PEs, 128 of 2KByte RAMs, and one 16 bit RISC Control Processor, into a single chip. The PE instruction set is enhanced for supporting 1DC codes. IMAP-CE is evaluated mainly by comparing its performance running 1DC codes with that of a 2.4GHz Intel P4 running optimized C codes. Based on the use of parallelizing techniques, benchmark results show a speedup of up to 20 for image filter kernels, and of 4 for a full image recognition application.

Siddiqi Irfan - One of the best experts on this subject based on the ideXlab platform.

  • Understanding Quantum Control Processor Capabilities and Limitations through Circuit Characterization
    eScholarship University of California, 2020
    Co-Authors: Butko Anastasiia, Michelogiannakis George, Williams Samuel, Iancu Costin, Donofrio David, Shalf John, Carter Jonathan, Siddiqi Irfan
    Abstract:

    Continuing the scaling of quantum computers hinges on building classical Control hardware pipelines that are scalable, extensible, and provide real time response. The instruction set architecture (ISA) of the Control Processor provides functional abstractions that map high-level semantics of quantum programming languages to low-level pulse generation by hardware. In this paper, we provide a methodology to quantitatively assess the effectiveness of the ISA to encode quantum circuits for intermediate-scale quantum devices with O($10^2$) qubits. The characterization model that we define reflects performance, the ability to meet timing constraint implications, scalability for future quantum chips, and other important considerations making them useful guides for future designs. Using our methodology, we propose scalar (QUASAR) and vector (qV) quantum ISAs as extensions and compare them with other ISAs in metrics such as circuit encoding efficiency, the ability to meet real-time gate cycle requirements of quantum chips, and the ability to scale to more qubits

  • Understanding Quantum Control Processor Capabilities and Limitations through Circuit Characterization
    'Institute of Electrical and Electronics Engineers (IEEE)', 2020
    Co-Authors: Butko Anastasiia, Michelogiannakis George, Williams Samuel, Iancu Costin, Donofrio David, Shalf John, Carter Jonathan, Siddiqi Irfan
    Abstract:

    Continuing the scaling of quantum computers hinges on building classical Control hardware pipelines that are scalable, extensible, and provide real time response. The instruction set architecture (ISA) of the Control Processor provides functional abstractions that map high-level semantics of quantum programming languages to low-level pulse generation by hardware. In this paper, we provide a methodology to quantitatively assess the effectiveness of the ISA to encode quantum circuits for intermediate-scale quantum devices with O($10^2$) qubits. The characterization model that we define reflects performance, the ability to meet timing constraint implications, scalability for future quantum chips, and other important considerations making them useful guides for future designs. Using our methodology, we propose scalar (QUASAR) and vector (qV) quantum ISAs as extensions and compare them with other ISAs in metrics such as circuit encoding efficiency, the ability to meet real-time gate cycle requirements of quantum chips, and the ability to scale to more qubits.Comment: 10 pages, 8 figure

  • Understanding Quantum Control Processor Capabilities and Limitations through Circuit Characterization
    2019
    Co-Authors: Butko Anastasiia, Michelogiannakis George, Williams Samuel, Iancu Costin, Donofrio David, Shalf John, Carter Jonathan, Siddiqi Irfan
    Abstract:

    Building usable quantum computers hinges on building a classical Control hardware pipeline that is scalable, extensible, and provides real time response. The Control Processor part of this pipeline provides functionality to map between the high-level quantum programming languages and low-level pulse generation using Arbitrary Waveform Generators. In this paper, we discuss design alternatives with an emphasis on supporting intermediate-scale quantum devices, with O(10^2) qubits. We introduce a methodology to assess the efficacy of a quantum ISA to encode quantum circuits. We use this methodology to evaluate several design points: RISC-like, vectors, and VLIW-like. We propose two quantum extensions to the broadly used open RISC-V ISA. Given the rapid rate of change in the quantum hardware pipeline, our open-source implementation provides a good starting point for design space experimentation, while our metrics can be independently used to guide design decisions.Comment: 11 pages, 10 figure

Butko Anastasiia - One of the best experts on this subject based on the ideXlab platform.

  • Understanding Quantum Control Processor Capabilities and Limitations through Circuit Characterization
    eScholarship University of California, 2020
    Co-Authors: Butko Anastasiia, Michelogiannakis George, Williams Samuel, Iancu Costin, Donofrio David, Shalf John, Carter Jonathan, Siddiqi Irfan
    Abstract:

    Continuing the scaling of quantum computers hinges on building classical Control hardware pipelines that are scalable, extensible, and provide real time response. The instruction set architecture (ISA) of the Control Processor provides functional abstractions that map high-level semantics of quantum programming languages to low-level pulse generation by hardware. In this paper, we provide a methodology to quantitatively assess the effectiveness of the ISA to encode quantum circuits for intermediate-scale quantum devices with O($10^2$) qubits. The characterization model that we define reflects performance, the ability to meet timing constraint implications, scalability for future quantum chips, and other important considerations making them useful guides for future designs. Using our methodology, we propose scalar (QUASAR) and vector (qV) quantum ISAs as extensions and compare them with other ISAs in metrics such as circuit encoding efficiency, the ability to meet real-time gate cycle requirements of quantum chips, and the ability to scale to more qubits

  • Understanding Quantum Control Processor Capabilities and Limitations through Circuit Characterization
    'Institute of Electrical and Electronics Engineers (IEEE)', 2020
    Co-Authors: Butko Anastasiia, Michelogiannakis George, Williams Samuel, Iancu Costin, Donofrio David, Shalf John, Carter Jonathan, Siddiqi Irfan
    Abstract:

    Continuing the scaling of quantum computers hinges on building classical Control hardware pipelines that are scalable, extensible, and provide real time response. The instruction set architecture (ISA) of the Control Processor provides functional abstractions that map high-level semantics of quantum programming languages to low-level pulse generation by hardware. In this paper, we provide a methodology to quantitatively assess the effectiveness of the ISA to encode quantum circuits for intermediate-scale quantum devices with O($10^2$) qubits. The characterization model that we define reflects performance, the ability to meet timing constraint implications, scalability for future quantum chips, and other important considerations making them useful guides for future designs. Using our methodology, we propose scalar (QUASAR) and vector (qV) quantum ISAs as extensions and compare them with other ISAs in metrics such as circuit encoding efficiency, the ability to meet real-time gate cycle requirements of quantum chips, and the ability to scale to more qubits.Comment: 10 pages, 8 figure

  • Understanding Quantum Control Processor Capabilities and Limitations through Circuit Characterization
    2019
    Co-Authors: Butko Anastasiia, Michelogiannakis George, Williams Samuel, Iancu Costin, Donofrio David, Shalf John, Carter Jonathan, Siddiqi Irfan
    Abstract:

    Building usable quantum computers hinges on building a classical Control hardware pipeline that is scalable, extensible, and provides real time response. The Control Processor part of this pipeline provides functionality to map between the high-level quantum programming languages and low-level pulse generation using Arbitrary Waveform Generators. In this paper, we discuss design alternatives with an emphasis on supporting intermediate-scale quantum devices, with O(10^2) qubits. We introduce a methodology to assess the efficacy of a quantum ISA to encode quantum circuits. We use this methodology to evaluate several design points: RISC-like, vectors, and VLIW-like. We propose two quantum extensions to the broadly used open RISC-V ISA. Given the rapid rate of change in the quantum hardware pipeline, our open-source implementation provides a good starting point for design space experimentation, while our metrics can be independently used to guide design decisions.Comment: 11 pages, 10 figure

Shorin Kyo - One of the best experts on this subject based on the ideXlab platform.

  • an integrated memory array Processor architecture for embedded image recognition systems
    International Symposium on Computer Architecture, 2005
    Co-Authors: Shorin Kyo, Shinichiro Okazaki, Tamio Arai
    Abstract:

    Embedded Processors for video image recognition require to address both the cost (die size and power) versus real-time performance issue, and also to achieve high flexibility due to the immense diversity of recognition targets, situations, and applications. This paper describes IMAP, a highly parallel SIMD linear Processor and memory array architecture that addresses these trading-off requirements. By using parallel and systolic algorithmic techniques, despite of its simple architecture IMAP achieves to exploit not only the straightforward per image row data level parallelism (DLP), but also the inherent DLP of other memory access patterns frequently found in various image recognition tasks, under the use of an explicit parallel C language (1DC). We describe and evaluate IMAP-CE, a latest IMAP Processor, which integrates 128 of 100MHz 8 bit4-way VLIW PEs, 128 of 2KByte RAMs, and one 16 bit RISC Control Processor, into a single chip. The PE instruction set is enhanced for supporting 1DC codes. IMAP-CE is evaluated mainly by comparing its performance running 1DC codes with that of a 2.4GHz Intel P4 running optimized C codes. Based on the use of parallelizing techniques, benchmark results show a speedup of up to 20 for image filter kernels, and of 4 for a full image recognition application.