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Ophir Frieder - One of the best experts on this subject based on the ideXlab platform.
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Feasibility of semiring-based Timing Constraints
ACM Transactions on Embedded Computing Systems, 2010Co-Authors: Shangping Ren, Ophir FriederAbstract:Real-time and embedded applications often involve different types of Timing Constraints, such as precedence Constraints and real-time Constraints. As real-time and embedded applications further advance, new Timing Constraint types are emerging as well. Recent research on interval-based Timing Constraints is an example. Thus, it is important to have a uniformed Timing Constraint representation so that a generalized approach can be developed to analyze the variant Constraint types. A semiring-based Timing Constraint model is introduced to generalize the representations of different Constraint types. Under this model, we develop an algorithm to check the satisfaction feasibility for a given set of semiring-based Timing Constraints. This algorithm provides better performance in the average case as compared to applying the Bellman-Ford algorithm directly on the Constraint set. In addition, for a set of feasible semiring-based Timing Constraints, event occurrence points that satisfy the Constraint set form a (hyperdimension) feasible region. For the given two sets of Timing Constraints, we develop a necessary and sufficient condition to testify whether the two Constraint sets' feasible regions have an inclusion relation. If one feasible region is included in the other, we know that the real-time event occurrences that satisfy the included Constraint set will necessarily satisfy the including set.
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prediction of Timing Constraint violation for real time embedded systems with known transient hardware failure distribution model
Real-Time Systems Symposium, 2006Co-Authors: Yue Yu, Ophir FriederAbstract:We apply interval-based Timing Constraint satisfaction probability results to predict Timing Constraint violations in real-time embedded system with a known hardware transient failure model. A previous study indicated that hardware transient failures follow a Poisson distribution with an average failure arrival rate lambda. Under this model, the distribution of time intervals between successive failures follows an exponential distribution with the same parameter lambda. Our goal is to use the statistical transient failure models to calculate the earliest time at which we can predict, with a determined level of confidence, that a given Timing Constraint may be violated. This earlier prediction provides time-critical systems with valuable time before the deadline is reached to adapt themselves, and hence, to minimize possible negative impacts caused by Timing Constraint violations
Tatsuo Ohtsuki - One of the best experts on this subject based on the ideXlab platform.
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A SIMD Instruction Set and Functional Unit Synthesis Algorithm with SIMD Operation Decomposition
IEICE Transactions on Information and Systems, 2005Co-Authors: Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo OhtsukiAbstract:This paper focuses on SIMD processor synthesis and proposes a SIMD instruction set/functional unit synthesis algorithm. Given an initial assembly code and a Timing Constraint, the proposed algorithm synthesizes an area-optimized processor core with optimal SIMD functional units. It also synthesizes a SIMD instruction set. The input initial assembly code is assumed to run on a full-resource SIMD processor (virtual processor) which has all the possible SIMD functional units. In our algorithm, we introduce the SIMD operation decomposition and apply it to the initial assembly code and the full-resource SIMD processor. By gradually reducing SIMD operations or decomposing SIMD operations, we can finally find a processor core with small area under the given Timing Constraint. The promising experimental results are also shown.
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Sub-operation Parallelism Optimization in SIMD Processor Core Synthesis
IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, 2005Co-Authors: Hideki Kawazu, Yuichiro Miyaoka, Masao Yanagisawa, Nozomu Togawa, Jumpei Uchida, Tatsuo OhtsukiAbstract:A b-bit SIMD functional unit has nk-bit sub-functional units in itself, where b = k × n. It can execute n-parallel k-bit operations. However, all the b-bit functional units in a processor core do not necessarily execute n-parallel operations. Depending on an application program, some of them just execute n/2-parallel operations or even n/4-parallel operations. This means that we can modify a b-bit SIMD functional unit so that it has n/2 k-bit sub-functional units or n/4 k-bit sub-functional units. The number of k-bit sub-functional units in a SIMD functional unit is called sub-operation parallelism. We incorporate a sub-operation parallelism optimization algorithm into SIMD functional unit optimization. Our proposed algorithm gradually reduces sub-operation parallelism of a SIMD functional unit while the Timing Constraint of execution time satisfied. Thereby, we can finally find a processor core with small area under the given Timing Constraint. We expect that we can obtain processor core configurations of smaller area in the same Timing Constraint rather than a conventional system. The promising experimental results are also shown.
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ASP-DAC - A hardware/software partitioning algorithm for SIMD processor cores
Proceedings of the 2003 conference on Asia South Pacific design automation - ASPDAC, 2003Co-Authors: Koichi Tachikake, Jinku Choi, Yuichiro Miyaoka, Masao Yanagisawa, Nozomu Togawa, Tatsuo OhtsukiAbstract:This paper proposes a new hardware/software partitioning algorithm for processor cores with SIMD instructions. Given a compiled assembly code including SIMD instructions, a Timing Constraint of execution time, and available hardware units, the proposed algorithm synthesizes an area-optimized processor core with a new assembly code. Firstly, we assume an initial processor core on which an input assembly code can run with the shortest execution time. Secondly we reduce a hardware unit added to a processor core one by one while the Timing Constraint is satisfied. At the same time, we update the assembly code so that it can run on the new processor configuration. By repeating this process, we finally obtain a processor core architecture with small area under the given Timing Constraint. We expect that vie can obtain a processor core which has appropriate SIMD functional units for running the input application program. The promising experimental results are also shown.
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A hardware/software partitioning algorithm for digital signal processor cores with two types of register files
IEEE APCCAS 2000. 2000 IEEE Asia-Pacific Conference on Circuits and Systems. Electronic Communication Systems. (Cat. No.00EX394), 1Co-Authors: Nozomu Togawa, Masao Yanagisawa, T. Sakurai, Tatsuo OhtsukiAbstract:Given a compiled assembly code and a Timing Constraint of execution time, the proposed algorithm generates a processor core configuration with a new assembly code running on the generated processor core. The proposed algorithm considers two register files and determines the number of registers in each of the register files. Moreover the algorithm considers two or more functional units for each arithmetic or logical operation and assigns functional units with small area to a processor core without causing performance penalty. A generated processor core will have small area compared with processor cores which have a single register file or those which have only one functional unit for each operation. The experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.
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ASP-DAC - Instruction set and functional unit synthesis for SIMD processor cores
ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753), 1Co-Authors: Nozomu Togawa, Koichi Tachikake, Yuichiro Miyaoka, Masao Yanagisawa, Tatsuo OhtsukiAbstract:This paper focuses on SIMD processor synthesis and proposes a SIMD instruction set/functional unit synthesis algorithm. Given an initial assembly code and a Timing Constraint, the proposed algorithm synthesizes an area-optimized processor core with optimal SIMD functional units. It also synthesizes a SIMD instruction set. The input initial assembly code is assumed to run on a full-resource SIMD processor (virtual processor) which has all the possible SIMD functional units. In our algorithm, we introduce the SIMD operation decomposition and apply it to the initial assembly code and the full-resource SIMD processor. By gradually reducing SIMD operations or decomposing SIMD operations, we can finally find a processor core with small area under the given Timing Constraint. The promising experimental results are also shown.
Jeffrey J P Tsai - One of the best experts on this subject based on the ideXlab platform.
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verifying Timing properties for distributed real time systems using Timing Constraint petri nets
Computer Software and Applications Conference, 1996Co-Authors: Jeffrey J P Tsai, S J Yang, Yaohsiung Chang, E Y T JuanAbstract:Timing analysis is essential to the development of valid computer systems especially for a distributed real-time system. We present both static and dynamic analysis procedures to verify Timing properties of distributed real-time systems using Timing Constraint Petri nets (TCPNs). With both derived static information and collected dynamic data, we can locate a faulty task in a distributed real-time system using a Timing behavior cross reference task. After a faulty task has been pinpointed the causes of a Timing Constraint violation in a faulty task can be identified.
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debugging for Timing Constraint violations
IEEE Software, 1996Co-Authors: Jeffrey J P Tsai, Jennhwa S YangAbstract:Analysts debug real-time distributed systems by viewing Timing behavior in the context of four possible faults. Animations and graphs of execution history make it easy to see process interactions. By applying a method to determine which fault caused the violation, analysts can go beyond Timing analysis to efficiently correct the program.
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Timing Constraint Petri nets and their application to schedulability analysis of real-time system specifications
IEEE Transactions on Software Engineering, 1995Co-Authors: Jeffrey J P Tsai, S J Yang, Yaohsiung ChangAbstract:We present Timing Constraint Petri nets (or TCPN's for short) and describe how to use them to model a real-time system specification and determine whether the specification is schedulable with respect to imposed Timing Constraints. The strength of TCPN's over other time-related Petri nets is in the modeling and analysis of conflict structures. Schedulability analysis is conducted in three steps: specification modeling, reachability simulation, and Timing analysis. First, we model a real-time system by transforming its system specification along with its imposed Timing Constraints into a TCPN; we call this net N/sub s/. Then we simulate the reachability of N/sub s/ to verify whether a marking, M/sub n/, is reachable from an initial marking, M/sub o/. It is important to note that a reachable marking in Petri nets is not necessarily reachable in TCPN's due to the imposed Timing Constraints, Therefore, in the Timing analysis step, a reachable marking M/sub n/, found in the reachability simulation step is analyzed to verify whether M/sub n/, is reachable with the Timing Constraints. M/sub n/ is said to be reachable in the TCPN's if and only if we can find at least one firing sequence /spl sigma/ so that all transitions in /spl sigma/ are strongly schedulable with respect to M/sub o/ under the Timing Constraints. If such M/sub n/ can be found, then we can assert that the specification is schedulable under the imposed Timing Constraints, otherwise the system specification needs to be modified or the Timing Constraints need to be relaxed. We also present a synthesis method for determining the best approximation of the earliest fire beginning time (EFBT) and the latest fire ending time (LFET) of each strongly schedulable transition. >
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Schedulability analysis of real-time systems using Timing Constraint Petri nets
1993 CompEuro Proceedings Computers in Design Manufacturing and Production, 1Co-Authors: Jeffrey J P Tsai, S J Yang, Y.-h. ChangAbstract:Timing Constraint Petri nets (TCPNs) to facilitate the modeling and analysis of real-time systems are presented. The schedulability analysis capabilities of TCPNs are discussed. Through modeling, analysis, and iterative refinement, the software developer can verify whether an underlying specification will be schedulable with respect to the given Timing requirements, all via the token game played in TCPNs. The schedulability of real-time systems against the imposed Timing Constraints is analyzed. >
Yushun Fan - One of the best experts on this subject based on the ideXlab platform.
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schedulability analysis method of Timing Constraint petri nets
Tsinghua Science & Technology, 2012Co-Authors: Yushun FanAbstract:Timing Constraints Petri Nets (TCPN) can be used to model a real-time system specification and to verify the Timing behavior of the system. This paper describes the limitations of the reachability analysis method in analyzing complex systems for existing TCPN. After doing further research on the schedulability analysis method with various topology structures, a more general state reachability analysis method is proposed. For various requirements of timely response for actual systems, this paper puts forward a heuristic method for selecting decision-spans of transitions and develop a heuristic algorithm for schedulability analysis of TCPN's. Examples are given to show the practicality of the method in the schedulability analysis for real time systems with various structures.
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Timing Constraint workflow nets for workflow analysis
IEEE Transactions on Systems Man and Cybernetics - Part A: Systems and Humans, 2003Co-Authors: Yushun Fan, Mengchu ZhouAbstract:The analysis of the correctness and rationality of a workflow model plays an important role in the research of workflow techniques and successful implementation of workflow management. This paper points out the relevant problems in the verification and analysis of a workflow model. It discusses two important properties: schedulability and boundedness of a workflow model considering Timing Constraints. To specify the Timing Constraints, WorkFlow net is extended with time information, leading to Timing Constraint workflow net (TCWF-net). This paper presents a model mapping method to convert a directed network graph (DNG) based workflow model, which is built by a graphic process modeling language extended with time information, into a TCWF-net. It then discusses its schedulability verification and synthesis. An algorithm to decompose an acyclic and free-choice TCWF-net into a set of T-components is presented, followed by a boundedness verification method. The usefulness of the research results is illustrated by an example.
Mengchu Zhou - One of the best experts on this subject based on the ideXlab platform.
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Timing Constraint workflow nets for workflow analysis
IEEE Transactions on Systems Man and Cybernetics - Part A: Systems and Humans, 2003Co-Authors: Yushun Fan, Mengchu ZhouAbstract:The analysis of the correctness and rationality of a workflow model plays an important role in the research of workflow techniques and successful implementation of workflow management. This paper points out the relevant problems in the verification and analysis of a workflow model. It discusses two important properties: schedulability and boundedness of a workflow model considering Timing Constraints. To specify the Timing Constraints, WorkFlow net is extended with time information, leading to Timing Constraint workflow net (TCWF-net). This paper presents a model mapping method to convert a directed network graph (DNG) based workflow model, which is built by a graphic process modeling language extended with time information, into a TCWF-net. It then discusses its schedulability verification and synthesis. An algorithm to decompose an acyclic and free-choice TCWF-net into a set of T-components is presented, followed by a boundedness verification method. The usefulness of the research results is illustrated by an example.