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Remus Teodorescu - One of the best experts on this subject based on the ideXlab platform.
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temperature dependency analysis and correction methods of in situ power loss estimation for Crystalline Silicon Modules undergoing potential induced degradation stress testing
Progress in Photovoltaics, 2015Co-Authors: Sergiu Spataru, Peter Hacke, Dezso Sera, Corinne E Packard, Tamas Kerekes, Remus TeodorescuAbstract:We propose a method for in situ characterization of the photovoltaic Module power at standard test conditions, using superposition of the dark current-voltage (I-V) curve measured at the elevated stress temperature, during potential-induced degradation (PID) testing. PID chamber studies were performed on several Crystalline Silicon Module designs to determine the extent to which the temperature dependency of maximum power is affected by the degradation of the Modules. The results using the superposition principle show a mismatch between the power degradation measured at stress temperature and the degradation measured at 25 °C, dependent on Module design, stress temperature, and level of degradation. We investigate the correction of this mismatch using two maximum-power temperature translation methods found in the literature. For the first method, which is based on the maximum-power temperature coefficient, we find that the temperature coefficient changes as the Module degrades by PID, thus limiting its applicability. The second method investigated is founded on the two-diode model, which allows for fundamental analysis of the degradation, but does not lend itself to large-scale data collection and analysis. Last, we propose and validate experimentally a simpler and more accurate maximum-power temperature translation method, by taking advantage of the near-linear relationship between the mismatch and power degradation. This method reduces test duration and cost, avoids stress transients while ramping to and from the stress temperature, eliminates flash testing except at the initial and final data points, and enables significantly faster and more detailed acquisition of statistical data for future application of various statistical reliability models. Potential-induced degradation chamber studies on Crystalline Silicon photovoltaic Modules show a mismatch between the power degradation measured at stress temperature and the power degradation measured at 25 °C, which depends on Module design, stress temperature, and level of degradation. We propose a method of in situ characterization of the photovoltaic Module power at standard test conditions using superposition of the dark I-V curve measured at the elevated stress temperature during potential-induced degradation testing, avoiding stress transients while ramping to and from the stress temperature
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Temperature‐dependency analysis and correction methods of in situ power‐loss estimation for Crystalline Silicon Modules undergoing potential‐induced degradation stress testing
Progress in Photovoltaics: Research and Applications, 2015Co-Authors: Sergiu Spataru, Peter Hacke, Dezso Sera, Corinne E Packard, Tamas Kerekes, Remus TeodorescuAbstract:We propose a method for in situ characterization of the photovoltaic Module power at standard test conditions, using superposition of the dark current-voltage (I-V) curve measured at the elevated stress temperature, during potential-induced degradation (PID) testing. PID chamber studies were performed on several Crystalline Silicon Module designs to determine the extent to which the temperature dependency of maximum power is affected by the degradation of the Modules. The results using the superposition principle show a mismatch between the power degradation measured at stress temperature and the degradation measured at 25 °C, dependent on Module design, stress temperature, and level of degradation. We investigate the correction of this mismatch using two maximum-power temperature translation methods found in the literature. For the first method, which is based on the maximum-power temperature coefficient, we find that the temperature coefficient changes as the Module degrades by PID, thus limiting its applicability. The second method investigated is founded on the two-diode model, which allows for fundamental analysis of the degradation, but does not lend itself to large-scale data collection and analysis. Last, we propose and validate experimentally a simpler and more accurate maximum-power temperature translation method, by taking advantage of the near-linear relationship between the mismatch and power degradation. This method reduces test duration and cost, avoids stress transients while ramping to and from the stress temperature, eliminates flash testing except at the initial and final data points, and enables significantly faster and more detailed acquisition of statistical data for future application of various statistical reliability models. Potential-induced degradation chamber studies on Crystalline Silicon photovoltaic Modules show a mismatch between the power degradation measured at stress temperature and the power degradation measured at 25 °C, which depends on Module design, stress temperature, and level of degradation. We propose a method of in situ characterization of the photovoltaic Module power at standard test conditions using superposition of the dark I-V curve measured at the elevated stress temperature during potential-induced degradation testing, avoiding stress transients while ramping to and from the stress temperature
Corinne E Packard - One of the best experts on this subject based on the ideXlab platform.
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temperature dependency analysis and correction methods of in situ power loss estimation for Crystalline Silicon Modules undergoing potential induced degradation stress testing
Progress in Photovoltaics, 2015Co-Authors: Sergiu Spataru, Peter Hacke, Dezso Sera, Corinne E Packard, Tamas Kerekes, Remus TeodorescuAbstract:We propose a method for in situ characterization of the photovoltaic Module power at standard test conditions, using superposition of the dark current-voltage (I-V) curve measured at the elevated stress temperature, during potential-induced degradation (PID) testing. PID chamber studies were performed on several Crystalline Silicon Module designs to determine the extent to which the temperature dependency of maximum power is affected by the degradation of the Modules. The results using the superposition principle show a mismatch between the power degradation measured at stress temperature and the degradation measured at 25 °C, dependent on Module design, stress temperature, and level of degradation. We investigate the correction of this mismatch using two maximum-power temperature translation methods found in the literature. For the first method, which is based on the maximum-power temperature coefficient, we find that the temperature coefficient changes as the Module degrades by PID, thus limiting its applicability. The second method investigated is founded on the two-diode model, which allows for fundamental analysis of the degradation, but does not lend itself to large-scale data collection and analysis. Last, we propose and validate experimentally a simpler and more accurate maximum-power temperature translation method, by taking advantage of the near-linear relationship between the mismatch and power degradation. This method reduces test duration and cost, avoids stress transients while ramping to and from the stress temperature, eliminates flash testing except at the initial and final data points, and enables significantly faster and more detailed acquisition of statistical data for future application of various statistical reliability models. Potential-induced degradation chamber studies on Crystalline Silicon photovoltaic Modules show a mismatch between the power degradation measured at stress temperature and the power degradation measured at 25 °C, which depends on Module design, stress temperature, and level of degradation. We propose a method of in situ characterization of the photovoltaic Module power at standard test conditions using superposition of the dark I-V curve measured at the elevated stress temperature during potential-induced degradation testing, avoiding stress transients while ramping to and from the stress temperature
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Temperature‐dependency analysis and correction methods of in situ power‐loss estimation for Crystalline Silicon Modules undergoing potential‐induced degradation stress testing
Progress in Photovoltaics: Research and Applications, 2015Co-Authors: Sergiu Spataru, Peter Hacke, Dezso Sera, Corinne E Packard, Tamas Kerekes, Remus TeodorescuAbstract:We propose a method for in situ characterization of the photovoltaic Module power at standard test conditions, using superposition of the dark current-voltage (I-V) curve measured at the elevated stress temperature, during potential-induced degradation (PID) testing. PID chamber studies were performed on several Crystalline Silicon Module designs to determine the extent to which the temperature dependency of maximum power is affected by the degradation of the Modules. The results using the superposition principle show a mismatch between the power degradation measured at stress temperature and the degradation measured at 25 °C, dependent on Module design, stress temperature, and level of degradation. We investigate the correction of this mismatch using two maximum-power temperature translation methods found in the literature. For the first method, which is based on the maximum-power temperature coefficient, we find that the temperature coefficient changes as the Module degrades by PID, thus limiting its applicability. The second method investigated is founded on the two-diode model, which allows for fundamental analysis of the degradation, but does not lend itself to large-scale data collection and analysis. Last, we propose and validate experimentally a simpler and more accurate maximum-power temperature translation method, by taking advantage of the near-linear relationship between the mismatch and power degradation. This method reduces test duration and cost, avoids stress transients while ramping to and from the stress temperature, eliminates flash testing except at the initial and final data points, and enables significantly faster and more detailed acquisition of statistical data for future application of various statistical reliability models. Potential-induced degradation chamber studies on Crystalline Silicon photovoltaic Modules show a mismatch between the power degradation measured at stress temperature and the power degradation measured at 25 °C, which depends on Module design, stress temperature, and level of degradation. We propose a method of in situ characterization of the photovoltaic Module power at standard test conditions using superposition of the dark I-V curve measured at the elevated stress temperature during potential-induced degradation testing, avoiding stress transients while ramping to and from the stress temperature
Sergiu Spataru - One of the best experts on this subject based on the ideXlab platform.
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temperature dependency analysis and correction methods of in situ power loss estimation for Crystalline Silicon Modules undergoing potential induced degradation stress testing
Progress in Photovoltaics, 2015Co-Authors: Sergiu Spataru, Peter Hacke, Dezso Sera, Corinne E Packard, Tamas Kerekes, Remus TeodorescuAbstract:We propose a method for in situ characterization of the photovoltaic Module power at standard test conditions, using superposition of the dark current-voltage (I-V) curve measured at the elevated stress temperature, during potential-induced degradation (PID) testing. PID chamber studies were performed on several Crystalline Silicon Module designs to determine the extent to which the temperature dependency of maximum power is affected by the degradation of the Modules. The results using the superposition principle show a mismatch between the power degradation measured at stress temperature and the degradation measured at 25 °C, dependent on Module design, stress temperature, and level of degradation. We investigate the correction of this mismatch using two maximum-power temperature translation methods found in the literature. For the first method, which is based on the maximum-power temperature coefficient, we find that the temperature coefficient changes as the Module degrades by PID, thus limiting its applicability. The second method investigated is founded on the two-diode model, which allows for fundamental analysis of the degradation, but does not lend itself to large-scale data collection and analysis. Last, we propose and validate experimentally a simpler and more accurate maximum-power temperature translation method, by taking advantage of the near-linear relationship between the mismatch and power degradation. This method reduces test duration and cost, avoids stress transients while ramping to and from the stress temperature, eliminates flash testing except at the initial and final data points, and enables significantly faster and more detailed acquisition of statistical data for future application of various statistical reliability models. Potential-induced degradation chamber studies on Crystalline Silicon photovoltaic Modules show a mismatch between the power degradation measured at stress temperature and the power degradation measured at 25 °C, which depends on Module design, stress temperature, and level of degradation. We propose a method of in situ characterization of the photovoltaic Module power at standard test conditions using superposition of the dark I-V curve measured at the elevated stress temperature during potential-induced degradation testing, avoiding stress transients while ramping to and from the stress temperature
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Temperature‐dependency analysis and correction methods of in situ power‐loss estimation for Crystalline Silicon Modules undergoing potential‐induced degradation stress testing
Progress in Photovoltaics: Research and Applications, 2015Co-Authors: Sergiu Spataru, Peter Hacke, Dezso Sera, Corinne E Packard, Tamas Kerekes, Remus TeodorescuAbstract:We propose a method for in situ characterization of the photovoltaic Module power at standard test conditions, using superposition of the dark current-voltage (I-V) curve measured at the elevated stress temperature, during potential-induced degradation (PID) testing. PID chamber studies were performed on several Crystalline Silicon Module designs to determine the extent to which the temperature dependency of maximum power is affected by the degradation of the Modules. The results using the superposition principle show a mismatch between the power degradation measured at stress temperature and the degradation measured at 25 °C, dependent on Module design, stress temperature, and level of degradation. We investigate the correction of this mismatch using two maximum-power temperature translation methods found in the literature. For the first method, which is based on the maximum-power temperature coefficient, we find that the temperature coefficient changes as the Module degrades by PID, thus limiting its applicability. The second method investigated is founded on the two-diode model, which allows for fundamental analysis of the degradation, but does not lend itself to large-scale data collection and analysis. Last, we propose and validate experimentally a simpler and more accurate maximum-power temperature translation method, by taking advantage of the near-linear relationship between the mismatch and power degradation. This method reduces test duration and cost, avoids stress transients while ramping to and from the stress temperature, eliminates flash testing except at the initial and final data points, and enables significantly faster and more detailed acquisition of statistical data for future application of various statistical reliability models. Potential-induced degradation chamber studies on Crystalline Silicon photovoltaic Modules show a mismatch between the power degradation measured at stress temperature and the power degradation measured at 25 °C, which depends on Module design, stress temperature, and level of degradation. We propose a method of in situ characterization of the photovoltaic Module power at standard test conditions using superposition of the dark I-V curve measured at the elevated stress temperature during potential-induced degradation testing, avoiding stress transients while ramping to and from the stress temperature
Peter Hacke - One of the best experts on this subject based on the ideXlab platform.
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Modeling current transfer from PV Modules based on meteorological data
2016 IEEE 43rd Photovoltaic Specialists Conference (PVSC), 2016Co-Authors: Peter Hacke, Sarah Kurtz, Ryan Smith, Dirk Jordan, John WohlgemuthAbstract:Current transferred from the active cell circuit to ground in Modules undergoing potential-induced degradation (PID) stress is analyzed with respect to meteorological data. Duration and coulombs transferred as a function of whether the Module is wet (from dew or rain) or the extent of uncondensed surface humidity are quantified based on meteorological indicators. With this, functions predicting the mode and rate of coulomb transfer are developed for use in estimating the relative PID stress associated with temperature, moisture, and system voltage in any climate. Current transfer in a framed Crystalline Silicon Module is relatively high when there is no condensed water on the Module, whereas current transfer in a thin-film Module held by edge clips is not, and displays a greater fraction of coulombs transferred when wet compared to the framed Module in the natural environment.
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temperature dependency analysis and correction methods of in situ power loss estimation for Crystalline Silicon Modules undergoing potential induced degradation stress testing
Progress in Photovoltaics, 2015Co-Authors: Sergiu Spataru, Peter Hacke, Dezso Sera, Corinne E Packard, Tamas Kerekes, Remus TeodorescuAbstract:We propose a method for in situ characterization of the photovoltaic Module power at standard test conditions, using superposition of the dark current-voltage (I-V) curve measured at the elevated stress temperature, during potential-induced degradation (PID) testing. PID chamber studies were performed on several Crystalline Silicon Module designs to determine the extent to which the temperature dependency of maximum power is affected by the degradation of the Modules. The results using the superposition principle show a mismatch between the power degradation measured at stress temperature and the degradation measured at 25 °C, dependent on Module design, stress temperature, and level of degradation. We investigate the correction of this mismatch using two maximum-power temperature translation methods found in the literature. For the first method, which is based on the maximum-power temperature coefficient, we find that the temperature coefficient changes as the Module degrades by PID, thus limiting its applicability. The second method investigated is founded on the two-diode model, which allows for fundamental analysis of the degradation, but does not lend itself to large-scale data collection and analysis. Last, we propose and validate experimentally a simpler and more accurate maximum-power temperature translation method, by taking advantage of the near-linear relationship between the mismatch and power degradation. This method reduces test duration and cost, avoids stress transients while ramping to and from the stress temperature, eliminates flash testing except at the initial and final data points, and enables significantly faster and more detailed acquisition of statistical data for future application of various statistical reliability models. Potential-induced degradation chamber studies on Crystalline Silicon photovoltaic Modules show a mismatch between the power degradation measured at stress temperature and the power degradation measured at 25 °C, which depends on Module design, stress temperature, and level of degradation. We propose a method of in situ characterization of the photovoltaic Module power at standard test conditions using superposition of the dark I-V curve measured at the elevated stress temperature during potential-induced degradation testing, avoiding stress transients while ramping to and from the stress temperature
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Temperature‐dependency analysis and correction methods of in situ power‐loss estimation for Crystalline Silicon Modules undergoing potential‐induced degradation stress testing
Progress in Photovoltaics: Research and Applications, 2015Co-Authors: Sergiu Spataru, Peter Hacke, Dezso Sera, Corinne E Packard, Tamas Kerekes, Remus TeodorescuAbstract:We propose a method for in situ characterization of the photovoltaic Module power at standard test conditions, using superposition of the dark current-voltage (I-V) curve measured at the elevated stress temperature, during potential-induced degradation (PID) testing. PID chamber studies were performed on several Crystalline Silicon Module designs to determine the extent to which the temperature dependency of maximum power is affected by the degradation of the Modules. The results using the superposition principle show a mismatch between the power degradation measured at stress temperature and the degradation measured at 25 °C, dependent on Module design, stress temperature, and level of degradation. We investigate the correction of this mismatch using two maximum-power temperature translation methods found in the literature. For the first method, which is based on the maximum-power temperature coefficient, we find that the temperature coefficient changes as the Module degrades by PID, thus limiting its applicability. The second method investigated is founded on the two-diode model, which allows for fundamental analysis of the degradation, but does not lend itself to large-scale data collection and analysis. Last, we propose and validate experimentally a simpler and more accurate maximum-power temperature translation method, by taking advantage of the near-linear relationship between the mismatch and power degradation. This method reduces test duration and cost, avoids stress transients while ramping to and from the stress temperature, eliminates flash testing except at the initial and final data points, and enables significantly faster and more detailed acquisition of statistical data for future application of various statistical reliability models. Potential-induced degradation chamber studies on Crystalline Silicon photovoltaic Modules show a mismatch between the power degradation measured at stress temperature and the power degradation measured at 25 °C, which depends on Module design, stress temperature, and level of degradation. We propose a method of in situ characterization of the photovoltaic Module power at standard test conditions using superposition of the dark I-V curve measured at the elevated stress temperature during potential-induced degradation testing, avoiding stress transients while ramping to and from the stress temperature
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application of the terrestrial photovoltaic Module accelerated test to failure protocol
Photovoltaic Specialists Conference, 2014Co-Authors: Peter Hacke, Kent Terwilliger, Sarah Kurtz, Ryan Smith, Stephen Glick, Greg Perrin, Nick Bosco, John H. WohlgemuthAbstract:The Terrestrial Photovoltaic Module Accelerated Test-to-Failure Protocol was applied to seven Crystalline Silicon Module types to test the durability of the various Module constructions on a quantitative basis in chamber and to evaluate the protocol itself. The Modules under test are subdivided into three accelerated lifetime testing paths: 85°C/85% relative humidity with system voltage bias, thermal cycling between − 40°C and 85°C, and paths that alternate between humidity with bias (one in each polarity) and thermal cycling. Three of the Module types were also fielded to ascertain degradation mechanisms occurring in the natural environment for comparison to the mechanisms seen in the accelerated testing. Potential induced-degradation in Modules negatively biased and Silicon nitride antireflective coating thinning on cells in Modules positively biased are among the important mechanisms that are seen both in the Modules stressed in the natural environment and in chamber. Junction box failure, cell breakage, and acid-assisted metallization degradation are included in the mechanisms seen in chamber tests, and they vary significantly between Module types. Per a goal of the accelerated test protocol, we found examples of Modules with components and process methods that showed degradation mechanisms that occurred faster than incumbents that had satisfactory field experience. These were evaluated as opportunities for durability improvement. Conversely, types that showed substantial improvement were also seen, especially with respect to system voltage stress durability.
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Results of IEC 62804 Draft Round Robin Testing (Presentation)
2013Co-Authors: Peter Hacke, Kent Terwilliger, G. Mathiak, J Berghold, Michael Koehl, S Hoffmann, T Weber, S Dietrich, S. Koch, M. EbertAbstract:Three Crystalline Silicon Module designs were distributed in five replicas each to five laboratories for testing according to the IEC 62804 (Committee Draft) system voltage durability qualification test for Crystalline Silicon photovoltaic (PV) Modules. The stress tests were performed in environmental chambers at 60 degrees C, 85% relative humidity, 96 h, and with Module nameplate system voltage applied.
Joshua M. Pearce - One of the best experts on this subject based on the ideXlab platform.
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Photovoltaic System Performance Enhancement With Nontracking Planar Concentrators: Experimental Results and Bidirectional Reflectance Function (BDRF)-Based Modeling
IEEE Journal of Photovoltaics, 2015Co-Authors: Rob W. Andrews, Andrew Pollard, Joshua M. PearceAbstract:Nontracking planar concentrators are a low-cost method of increasing the performance of traditional solar photovoltaic (PV) systems. This paper presents new methodologies for properly modeling this type of system using a bidirectional reflectance function for nonideal surfaces rather than traditional geometric optics. This methodology allows for the evaluation and optimization of specular and nonspecular reflectors in planar concentration systems. In addition, an outdoor system has been shown to improve energy yield by 45% for a traditional flat glass Module and by 40% for a prismatic glass Crystalline Silicon Module when compared with a control Module at the same orientation. When compared with a control Module set at the optimal tilt angle for this region, the energy improvement is 18% for both systems. Simulations show that a maximum increase of 30% is achievable for an optimized system located in Kingston, ON, Canada, using a reflector with specular reflection and an integrated hemispherical reflectance of 80%. This validated model can be used to optimize reflector topology to identify the potential for increased energy harvest from both existing PV and new-build PV assets.
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Photovoltaic system performance enhancement with non-tracking planar concentrators: Experimental results and BDRF based modelling
2013 IEEE 39th Photovoltaic Specialists Conference (PVSC), 2013Co-Authors: Rob W. Andrews, Andrew Pollard, Joshua M. PearceAbstract:Non-tracking planar concentrators are a low-cost method of increasing the performance of traditional solar photovoltaic (PV) systems. In this study such an outdoor system has been shown to improve energy yield by 45% for a traditional flat glass Module and by 35% for a prismatic glass Crystalline Silicon Module. In addition, this paper presents new methodologies for properly modelling this type of system design and experimental results using a bi-directional reflectance function (BDRF) of non-ideal surfaces rather than traditional geometric optics. This methodology allows for the evaluation and eventual optimization of specular and non-specular reflectors in planar concentration systems.