The Experts below are selected from a list of 18762 Experts worldwide ranked by ideXlab platform
Alberto Sangiovannivincentelli - One of the best experts on this subject based on the ideXlab platform.
-
synthesis of software programs for embedded control applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1999Co-Authors: Felice Balarin, Luciano Lavagno, Massimiliano Chiodo, Attila Jurecska, Ellen M Sentovich, Harry Hsieh, Alberto Sangiovannivincentelli, Paolo Giusto, Kei SuzukiAbstract:Software components for embedded reactive real-time applications must satisfy tight code size and run-time constraints. Cooperating finite state machines provide convenient intermediate format for embedded system co-synthesis, between high-level specification languages and software or hardware implementations. We propose a software generation methodology that takes advantage of a restricted class of specifications and allows for tight control over the implementation cost. The methodology exploits several techniques from the domain of Boolean function optimization. We also describe how the simplified control/Data-Flow Graph used as an intermediate representation can be used to accurately estimate the size and timing cost of the final executable code.
-
synthesis of software programs for embedded control application
Design Automation Conference, 1995Co-Authors: Massimiliano Chiodo, Luciano Lavagno, Paolo Guisto, Attila Jurecska, Ellen M Sentovich, Harry Hsieh, Kei Suzuki, Alberto SangiovannivincentelliAbstract:Software components for embedded reactive real-time applications must satisfy tight code size and run-time constraints. Cooperating Finite State Machines provide a convenient intermediate format for embedded system co-synthesis, between high-level specification languages and software or hardware implementations. We propose a software generation methodology that takes advantage of the very restricted class of specifications and allows for tight control over the implementation cost. The methodology exploits several techniques from the domain of Boolean function optimization. We also describe how the simplified control/Data-Flow Graph used as an intermediate representation can be used to accurately estimate the size and timing cost of the final executable code.
Chabong Choi - One of the best experts on this subject based on the ideXlab platform.
-
software synthesis for dynamic Data Flow Graph
Rapid System Prototyping, 1997Co-Authors: Chabong ChoiAbstract:Data Flow Graph is a useful computational model to describe the functionality of a digital system. To execute a Data Flow Graph on a target system, it should be synthesized to the code to be compiled on the target system. Current research activities on software synthesis are mainly focused on Synchronous Data Flow (SDF) Graph, which can not represent the control structure of the application. On the other hand, Dynamic Data Flow (DDF) Graph can express the control structure, such as conditionals and Data dependent iterations. This paper synthesizes a C code for a DDF Graph which includes not only the functions associated with the nodes of the Graph, but also the run-time scheduler and the run-time buffer manager which can execute a DDF Graph without deadlock with bounded memory requirement. In addition, this paper suggests hierarchical implementation of DDF which enhances the efficiency of run-time scheduling by clustering SDF type nodes as a specific macro node.
Michitaka Kameyama - One of the best experts on this subject based on the ideXlab platform.
-
program counter less bit serial field programmable vlsi processor with mesh connected cellular array structure
IEEE Computer Society Annual Symposium on VLSI, 2004Co-Authors: N Ohsawa, Masanori Hariyama, O Sakamoto, Michitaka KameyamaAbstract:This paper proposes a field programmable VLSI processor (FPVLSI) based on a bit-serial mesh-connected cellular array that reduces complexity of a programmable interconnection network. A cell is capable of performing operations, storing intermediate results, and controlling bit-serial operations. To implement these three functions efficiently, the cell consists of shift-register-based lookup tables. Moreover, direct allocation of a control/Data Flow Graph (CDFG) is employed where only a single node in a CDFG is mapped into a single cell so that the interconnection complexity is greatly reduced. The FPVLSI with 64 cells is designed in a 0.18/spl mu/m CMOS design rule. The estimated performance of the FPVLSI is evaluated to be 9 times higher than that of the conventional FPGA in a typical application.
-
a field programmable vlsi processor based on direct allocation of a control Data Flow Graph
Electronics and Communications in Japan Part Ii-electronics, 2004Co-Authors: N Ohsawa, Masanori Hariyama, Michitaka KameyamaAbstract:The next generation of information systems will require the development of special-purpose processors that can accommodate computation-intensive algorithms at superhigh speeds. Design methods based on field-programmable gate arrays (FPGA), which can guide the fabrication of special-use processors at lower cost than ad hoc design methods, are attracting increased attention. However, special-purpose processors based on FPGA have the problem of poor performance compared to processors designed by ad hoc methods. In this article, we propose to eliminate this problem with FPGA processors by using field-programmable VLSI (or FPVLSI) arrays of processing elements in which Data transfer takes place between nearest-neighbor processors only, direct allocation of control/Data Flow Graphs, and bit-serial architecture. Furthermore, we show that when this FPVLSI approach is used to implement a 16-point FFT, the resulting processor module is over 20 times faster than a currently available FPGA module with the same area. © 2004 Wiley Periodicals, Inc. Electron Comm Jpn Pt 2, 87(7): 28–37, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjb.10076
-
high performance field programmable vlsi processor based on a direct allocation of a control Data Flow Graph
IEEE Computer Society Annual Symposium on VLSI, 2002Co-Authors: N Ohsawa, Masanori Hariyama, Michitaka KameyamaAbstract:This paper proposes a high-performance field programmable VLSI processor (FPVLSI), in which a bit-serial processing element (PE) array is introduced to reduce the complexity of programmable interconnection networks. Therefore, the area and delay of a switch block in the interconnection network can be greatly reduced. Moreover, direct allocation of a control/Data Flow Graph is employed where only a single node is mapped into a PE so that the wiring complexity is greatly reduced. The FPVLSI with 4400 PEs is designed in a 0.35 /spl mu/m CMOS process. The performance of the FPVLSI is evaluated to be 28 times higher than that of the typical FPGA when executing the 16-point FFT.
Sanjoy Baruah - One of the best experts on this subject based on the ideXlab platform.
-
applying real time scheduling theory to the synchronous Data Flow model of computation
Euromicro Conference on Real-Time Systems, 2017Co-Authors: Abhishek Singh, Pontus Ekberg, Sanjoy BaruahAbstract:Schedulability analysis techniques that are well understood within the real-time scheduling community are applied to the analysis of recurrent real-time workloads that are modeled using the synchronous Data-Flow Graph (SDFG) model. An enhancement to the standard SDFG model is proposed, that permits the specification of a real-time latency constraint between a specified input and a specified output of an SDFG. A technique is derived for transforming such an enhanced SDFG to a collection of traditional 3-parameter sporadic tasks, thereby allowing for the analysis of systems of SDFG tasks using the methods and algorithms that have previously been developed within the real-time scheduling community for the analysis of systems of such sporadic tasks. The applicability of this approach is illustrated by applying prior results from real-time scheduling theory to construct an exact preemptive uniprocessor schedulability test for collections of recurrent processes that are each represented using the enhanced SDFG model.
Luciano Lavagno - One of the best experts on this subject based on the ideXlab platform.
-
realistic performance constrained pipelining in high level synthesis
Design Automation and Test in Europe, 2011Co-Authors: A Kondratyev, Luciano Lavagno, Mike Meyer, Yosinori WatanabeAbstract:This paper describes an approach to pipelining in high-level synthesis that modifies the control/Data Flow Graph before and after scheduling. This enables the direct re-use of a pre-existing, timing- and area-aware non-pipelined simultaneous scheduler and binder. Such an approach ensures that the RTL output can be synthesized within the given timing and area constraints. Results from real industrial designs show the effectiveness of this approach in improving Pareto optimality with respect to area, delay and power.
-
synthesis of software programs for embedded control applications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1999Co-Authors: Felice Balarin, Luciano Lavagno, Massimiliano Chiodo, Attila Jurecska, Ellen M Sentovich, Harry Hsieh, Alberto Sangiovannivincentelli, Paolo Giusto, Kei SuzukiAbstract:Software components for embedded reactive real-time applications must satisfy tight code size and run-time constraints. Cooperating finite state machines provide convenient intermediate format for embedded system co-synthesis, between high-level specification languages and software or hardware implementations. We propose a software generation methodology that takes advantage of a restricted class of specifications and allows for tight control over the implementation cost. The methodology exploits several techniques from the domain of Boolean function optimization. We also describe how the simplified control/Data-Flow Graph used as an intermediate representation can be used to accurately estimate the size and timing cost of the final executable code.
-
synthesis of software programs for embedded control application
Design Automation Conference, 1995Co-Authors: Massimiliano Chiodo, Luciano Lavagno, Paolo Guisto, Attila Jurecska, Ellen M Sentovich, Harry Hsieh, Kei Suzuki, Alberto SangiovannivincentelliAbstract:Software components for embedded reactive real-time applications must satisfy tight code size and run-time constraints. Cooperating Finite State Machines provide a convenient intermediate format for embedded system co-synthesis, between high-level specification languages and software or hardware implementations. We propose a software generation methodology that takes advantage of the very restricted class of specifications and allows for tight control over the implementation cost. The methodology exploits several techniques from the domain of Boolean function optimization. We also describe how the simplified control/Data-Flow Graph used as an intermediate representation can be used to accurately estimate the size and timing cost of the final executable code.
