Serial Architecture

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Michitaka Kameyama - One of the best experts on this subject based on the ideXlab platform.

  • Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture
    IEICE Transactions on Electronics, 2008
    Co-Authors: Masanori Hariyama, Shota Ishihara, Michitaka Kameyama
    Abstract:

    This paper presents a novel asynchronous Architecture of Field-programmable gate arrays (FPGAs) to reduce the power consumption. In the dynamic power consumption of the conventional FPGAs, the power consumed by the switch blocks and clock distribution is dominant since FPGAs have complex switch blocks and the large number of registers for high programmability. To reduce the power consumption of switch blocks and clock distribution, asynchronous bit-Serial Architecture is proposed. To ensure the correct operation independent of data-path lengths, we use the level-encoded dual-rail encoding and propose its area-efficient implementation. The proposed field-programmable VLSI is implemented in a 90nm CMOS technology. The delay and the power consumption of the proposed FPVLSI are respectively 61% and 58% of those of 4-phase dual-rail encoding which is the most common encoding in delay insensitive encoding.

  • PAPER Special Section on Advanced Processors Based on Novel Concepts in Computation Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture
    2008
    Co-Authors: Masanori Hariyama, Shota Ishihara, Michitaka Kameyama
    Abstract:

    SUMMARY This paper presents a novel asynchronous Architecture of Field-programmable gate arrays (FPGAs) to reduce the power consumption. In the dynamic power consumption of the conventional FPGAs, the power consumed by the switch blocks and clock distribution is dominant since FPGAs have complex switch blocks and the large number of registers for high programmability. To reduce the power consumption of switch blocks and clock distribution, asynchronous bit-Serial Architecture is proposed. To ensure the correct operation independent of data-path lengths, we use the level-encoded dual-rail encoding and propose its area-efficient implementation. The proposed field-programmable VLSI is implemented in a 90 nm CMOS technology. The delay and the power consumption of the proposed FPVLSI are respectively 61% and 58% of those of 4-phase dual-rail encoding which is the most common encoding in delay insensitive encoding.

  • A Field-programmable VLSI based on an asynchronous bit-Serial Architecture
    2007 IEEE Asian Solid-State Circuits Conference, 2007
    Co-Authors: Masanori Hariyama, Shota Ishihara, Chang Chia Wei, Michitaka Kameyama
    Abstract:

    This paper presents a novel asynchronous Architecture of field-programmable gate arrays (FPGAs) to reduce the power consumption. In the dynamic power consumption of the conventional FPGAs, the power consumed by the switch blocks and clock distribution is dominant since FPGAs have complex switch blocks and the large number of registers for high programmability. To reduce the power consumption of switch blocks and clock distribution, asynchronous bit-Serial Architecture is proposed. To ensure the correct operation independent of data-path lengths, we use the level-encoded dual-rail encoding and propose its area-efficient implementation. The proposed field-programmable VLSI is implemented in a 90 nm CMOS technology. The delay and the power consumption of the proposed FPVLSI are respectively 61% and 58% of those of 4-phase dual-rail encoding which is the most common encoding in delay sensitive encoding.

  • Design of a Multi-Context FPVLSI based on an Asynchronous Bit-Serial Architecture
    2007 6th IEEE Dallas Circuits and Systems Workshop on System-on-Chip, 2007
    Co-Authors: Waidyasooriya Hasitha Muthumala, Masanori Hariyama, Michitaka Kameyama
    Abstract:

    This paper presents a novel asynchronous bit-Serial Architecture for multi-context field programmable VLSIs (MC-FPVLSI), Conventional MC-FPVLSIs use global wires to distribute the context-ID signal. As a result, hardware utilization ratio decreases, since it is impossible to execute different contexts simultaneously. They also have a high power consumption and high area overhead due to the clock tree and context ID trees. The proposed MC-FPVLSI eliminates the clock tree and global context ID trees completely. It uses a locally distributed context-ID signal and therefore, partial reconfiguration and simultaneous execution of different contexts are possible. It also uses the same wires to transfer the data and context ID signal, so that the area can be reduced further. The proposed Architecture is designed using 6-metal 1-poly 90nm CMOS process technology.

  • Chip design of a field programmable VLSI processor using memory-based cells
    2003
    Co-Authors: N. Ohsawa, Masanori Hariyama, O. Sakamoto, Michitaka Kameyama
    Abstract:

    This paper proposes a field programmable VLSI processor (FPVLSI) based on bit-Serial Architecture that makes the utilized ratio of hardware components in the cell very high irrespective of the word length. Based on the regular data flow of bit-Serial Architecture, a lookup table implemented using a shift register is proposed for the cell. One of the functional unit, memory unit and control unit can be implemented using the same cell. As a result, area of the cell is reduced. The FPVLSI with 64 cells is designed in a 0.18 /spl mu/m CMOS design rule. The performance of the FPVLSI is evaluated to be 13 times higher than that of the conventional FPGA in a typical application.

Chaitali Chakrabarti - One of the best experts on this subject based on the ideXlab platform.

Philip H W Leong - One of the best experts on this subject based on the ideXlab platform.

  • Serial and Parallel FPGA-based Variable Block Size Motion Estimation Processors
    Journal of Signal Processing Systems, 2008
    Co-Authors: Philip H W Leong
    Abstract:

    H.264/AVC is the latest video coding standard adopting variable block size motion estimation (VBS-ME), quarter-pixel accuracy, motion vector prediction and multi-reference frames for motion estimation. These new features result in much higher computation requirements than previous coding standards. In this paper we propose a novel most significant bit (MSB) first bit-Serial Architecture for full-search block matching VBS-ME, and compare it with systolic implementations. Since the nature of MSB-first processing enables early termination of the sum of absolute difference (SAD) calculation, the average hardware performance can be enhanced. Five different designs, one and two dimensional systolic and tree implementations along with bit-Serial, are compared in terms of performance, pixel memory bandwidth, occupied area and power consumption.

  • a bit Serial implementation of the international data encryption algorithm idea
    Field-Programmable Custom Computing Machines, 2000
    Co-Authors: M P Leong, O Y H Cheung, K H Tsoi, Philip H W Leong
    Abstract:

    A high-performance implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. Using a novel bit-Serial Architecture to perform multiplication modulo 2/sup 16/+1, the implementation occupies a minimal amount of hardware. The bit-Serial Architecture enabled the algorithm to be deeply pipelined to achieve a system clock rate of 125 MHz on a Xilinx Virtex XCV300-6, delivering a throughput of 500 Mb/sec. With a XCV1000-6 device, the estimated performance is 2 Gb/sec, three orders of magnitude faster than a software implementation on a 450 MHz Intel Pentium II. This design is suitable for applications in on-line encryption for high-speed networks.

  • FCCM - A bit-Serial implementation of the international data encryption algorithm IDEA
    Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871), 1
    Co-Authors: M P Leong, O Y H Cheung, K H Tsoi, Philip H W Leong
    Abstract:

    A high-performance implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. Using a novel bit-Serial Architecture to perform multiplication modulo 2/sup 16/+1, the implementation occupies a minimal amount of hardware. The bit-Serial Architecture enabled the algorithm to be deeply pipelined to achieve a system clock rate of 125 MHz on a Xilinx Virtex XCV300-6, delivering a throughput of 500 Mb/sec. With a XCV1000-6 device, the estimated performance is 2 Gb/sec, three orders of magnitude faster than a software implementation on a 450 MHz Intel Pentium II. This design is suitable for applications in on-line encryption for high-speed networks.

Keshab K. Parhi - One of the best experts on this subject based on the ideXlab platform.

  • Digit-Serial Architecture
    Digit-Serial Computation, 1995
    Co-Authors: Richard Hartley, Keshab K. Parhi
    Abstract:

    Digital signal processing (DSP) is used in a wide range of applications such as speech, telephone, mobile radio, satellite communications, biomedical, image, video, radar and sonar. Different applications of signal processing impose different constraints on hardware Architectures. This book is concerned with design of real-time Architectures where signal samples are processed as soon as these are received from the signal source. This is in contrast with batch-mode processing where signal samples are first stored in buffers and then processed in batch. Real-time DSP Architectures are designed to match the hardware speed to the application sample speed. Since different real-time applications require different sample rates, a DSP algorithm needs to be implemented in different styles for various applications. Thus, design of real-time Architectures for these applications requires study of families of Architectures.

  • A systematic approach for design of digit-Serial signal processing Architectures
    IEEE Transactions on Circuits and Systems, 1991
    Co-Authors: Keshab K. Parhi
    Abstract:

    A systematic unfolding transformation technique for transforming bit-Serial Architecture into equivalent digit-Serial ones is presented. The novel feature of the unfolding technique lies in the generation of functionally correct control circuits in the digit-Serial Architectures. For some applications bit-Serial Architectures may be too slow, and bit-parallel Architectures may be faster than necessary and may require too much hardware. The desired sample rate in these applications can be achieved using the digit-Serial approach, where multiple bits of a sample are processed in a single clock cycle. The number of bits processed in one clock cycle in the digit-Serial systems is referred to as the digit size; the digit size can be any arbitrary integer (the digit size was restricted to be a divisor of wordlength in past ad hoc designs). Digit-Serial implementation of two's complement adders and multipliers is described. Least-significant-bit-first bit-Serial implementation of two's complement division, square-root, and compare-select operations are presented, and the corresponding digit-Serial Architectures for these operations are obtained using the unfolding algorithm. Unfolding of multiple-rate operations (such as interpolators and decimators) is also addressed. >

  • ISCAS - Folded VLSI Architectures for discrete wavelet transforms
    1993 IEEE International Symposium on Circuits and Systems, 1
    Co-Authors: Keshab K. Parhi, T. Nishitani
    Abstract:

    Two classes of novel folded VLSI Architectures are presented. They are the word-level folded Architecture and the bit-level folded or digit-Serial Architecture, for implementation of discrete wavelet transforms. In the word-level folded Architecture, the computations of all wavelet levels are folded to the same low-pass and high-pass filters. The number of registers in the folded Architecture is minimized by the use of generalized life time analysis. The advantage of the word-level folded Architecture is low latency, and its drawbacks are increased hardware area, less than 100% hardware utilization, and complex routing and interconnection required by the converters used in this Architecture. These drawbacks are eliminated in the alternate bit-level folded digit-Serial Architecture which requires simpler control circuits, routing, and interconnection, and achieves complete hardware utilization, at the expense of an increase in the system latency and some constraints on the wordlength. In latency-critical applications, the use of the word-level folded Architecture is proposed. If latency is not so critical, the use of the bit-level digit-Serial Architecture is proposed. >

L. Lucke - One of the best experts on this subject based on the ideXlab platform.

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