The Experts below are selected from a list of 6219 Experts worldwide ranked by ideXlab platform
Mario R Casu - One of the best experts on this subject based on the ideXlab platform.
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half buffer retiming and token cages for synchronous elastic circuits
Iet Computers and Digital Techniques, 2011Co-Authors: Mario R CasuAbstract:Synchronous elastic circuits borrow the tolerance of computation and communication latencies from the asynchronous design style. The Datapath is made elastic by turning registers into elastic buffers and adding a control layer that uses synchronous handshake signals and join/fork controllers. Join elements are the objective of two improvements discussed in this study. Half-buffer retiming allows the creation of input queues by relocating one of the latches of the elastic buffer which follows the join controller. Token cages improve the performance of join controllers that use the early-evaluation firing rule. Their effect on throughput is discussed by means of examples representative of typical topologies, simulations with synthetic benchmarks and a realistic microarchitecture. Area and power costs of the control logic and the possible impact on the Datapath are evaluated, based on the results of logic synthesis experiments on a 45 nm CMOS technology.
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improving synchronous elastic circuits token cages and half buffer retiming
Symposium on Asynchronous Circuits and Systems, 2010Co-Authors: Mario R CasuAbstract:Synchronous elastic circuits help synchronous designs tolerate computation or communication latencies, in a way similar to the asynchronous design style. The Datapath is made elastic by turning registers into elastic buffers and adding a control layer that uses handshake signals and join/fork controllers. Join elements are the objective of two improvements discussed in this paper. The first one is an elegant implementation of input by passable queues obtained by retiming one of the latches of the elastic buffer which follows the join controller. The second one enlarges the set of cases in which unneeded input tokens are discarded in join controllers with early evaluation. Their impact on throughput are discussed by means of examples representative of typical topologies and of a realistic processor Datapath. Their area and power costs are evaluated on a 45nm CMOS technology.
Gergely Pongracz - One of the best experts on this subject based on the ideXlab platform.
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toward a sweet spot of data plane programmability portability and performance on the scalability of multi architecture p4 pipelines
IEEE Journal on Selected Areas in Communications, 2018Co-Authors: Gyanesh P Patra, Fabricio Rodriguez E Cesen, Juan Sebastian Mejia, Daniel Lazkani Feferman, Levente Csikor, Christian Esteve Rothenberg, Gergely PongraczAbstract:Despite having received less attention compared to the control and application plane aspects of software-defined networking (SDN), the data plane is a critical piece of the puzzle. P4 takes SDN Datapaths to the next level by unlocking deep programmability through a target-independent high-level programming language that can be compiled to run on a variety of targets (e.g., ASIC, FPGA, and GPU). This paper presents the design and evaluation of our sweet spot approach on SDN Datapaths, offering three contending characteristics, namely, performance, portability, and scalability in multiple realistic scenarios. The focus is on our Multi-Architecture Compiler System for Abstract Data Planes proposal, which blends the high-level protocol-independent programmability of P4 with low-level but cross-platform (HW & SW) Application Programming Interfaces brought by OpenDataPlane, this way supporting many different vendors and architectures. Besides the performance evaluation for varying packet sizes and memory lookup tables, we investigate the impact of increasing pipeline complexity ranging from elemental L2 switching to more complex data center and border network gateways. We investigate the scalability for increasing the number of cores and evaluate a novel method for run-time core reallocation. Furthermore, we run experiments on different target platforms (e.g., $\times 86$ , ARM, 10G/100G), inducing different ways of packet mangling through specific drivers (e.g., DPDK and Netmap), and compare the results to state-of-the-art Datapath alternatives.
Maciej Ciesielski - One of the best experts on this subject based on the ideXlab platform.
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dag aware logic synthesis of Datapaths
Design Automation Conference, 2016Co-Authors: Maciej Ciesielski, Mihir Choudhury, Andrew SullivanAbstract:Traditional Datapath synthesis for standard-cell designs go through extraction of arithmetic operations from the high-level description, high-level synthesis, and netlist generation. In this paper, we take a fresh look at applying high-level synthesis methodologies in logic synthesis. We present a DAG-Aware synthesis technique for Datapaths synthesis which is implemented using And-Inv-Graphs. Our approach targets area minimization. The proposed algorithm includes identifying vector multiplexers, searching for common specification logic, and reallocating multiplexers in the Boolean network. We propose an algorithm to identify common specification logic by using subgraph isomorphism. Experimental results show that our technique can provide over 10% area reduction beyond the traditional design flow. The proposed algorithm is tested on industry designs and academic benchmark suits using IBM 14nm technology.
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Automatic word-level abstraction of Datapath
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016Co-Authors: Cunxi Yu, Maciej CiesielskiAbstract:Abstracting word information from gate-level designs is essential for formal verification, technology mapping and hardware security applications. In this paper, we present a novel method to abstract the word-level information from arithmetic gate-level circuits using a computer algebraic approach. The proposed technique translates the gate-level circuit into algebraic domain and applies algebraic rewriting to extract the arithmetic function. During the iterative rewriting, intermediate Pseudo-Boolean expressions are examined to identify word-level candidates. The proposed algorithm is able to abstract the word components from candidates and to reason about the word operation from the internal expressions. Successful experiments were performed on gate-level Datapaths, including multipliers of up to 128-bit widths.
Gyanesh P Patra - One of the best experts on this subject based on the ideXlab platform.
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toward a sweet spot of data plane programmability portability and performance on the scalability of multi architecture p4 pipelines
IEEE Journal on Selected Areas in Communications, 2018Co-Authors: Gyanesh P Patra, Fabricio Rodriguez E Cesen, Juan Sebastian Mejia, Daniel Lazkani Feferman, Levente Csikor, Christian Esteve Rothenberg, Gergely PongraczAbstract:Despite having received less attention compared to the control and application plane aspects of software-defined networking (SDN), the data plane is a critical piece of the puzzle. P4 takes SDN Datapaths to the next level by unlocking deep programmability through a target-independent high-level programming language that can be compiled to run on a variety of targets (e.g., ASIC, FPGA, and GPU). This paper presents the design and evaluation of our sweet spot approach on SDN Datapaths, offering three contending characteristics, namely, performance, portability, and scalability in multiple realistic scenarios. The focus is on our Multi-Architecture Compiler System for Abstract Data Planes proposal, which blends the high-level protocol-independent programmability of P4 with low-level but cross-platform (HW & SW) Application Programming Interfaces brought by OpenDataPlane, this way supporting many different vendors and architectures. Besides the performance evaluation for varying packet sizes and memory lookup tables, we investigate the impact of increasing pipeline complexity ranging from elemental L2 switching to more complex data center and border network gateways. We investigate the scalability for increasing the number of cores and evaluate a novel method for run-time core reallocation. Furthermore, we run experiments on different target platforms (e.g., $\times 86$ , ARM, 10G/100G), inducing different ways of packet mangling through specific drivers (e.g., DPDK and Netmap), and compare the results to state-of-the-art Datapath alternatives.
Kwangting Cheng - One of the best experts on this subject based on the ideXlab platform.
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using word level atpg and modular arithmetic constraint solving techniques for assertion property checking
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2001Co-Authors: Chungyang Huan, Kwangting ChengAbstract:We present a new approach to checking assertion properties for register-transfer level (RTL) design verification. Our approach combines structural word-level automatic test pattern generation (ATPG) and modular arithmetic constraint-solving techniques to solve the constraints imposed by the target assertion property. Our word-level ATPG and implication technique not only solves the constraints on the control logic, but also propagates the logic implications to the Datapath. A novel arithmetic constraint solver based on modular number system is then employed to solve the remaining constraints in Datapath. The advantages of the new method are threefold. First, the decision-making process of the word-lever ATPG is confined to the selected control signals only. Therefore, the enumeration of enormous number of choices at the Datapath signals is completely avoided. Second, our new implication translation techniques allow word-level logic implication being performed across the boundary of Datapath and control logic and, therefore, efficiently cut down the ATPG search space. Third, our arithmetic constraint solver is based on modular instead of integral number systems. It can thus avoid the false-negative effect resulting from the bit-vector value modulation. A prototype system has been built that consists of an industrial front-end hardware description language (HDL) parser, a property-to-constraint converter, and the ATPG/arithmetic constraint-solving engine. The experimental results on some public benchmark and industrial circuits demonstrate the efficiency of our approach and its applicability to large industrial designs.
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assertion checking by combined word level atpg and modular arithmetic constraint solving techniques
Design Automation Conference, 2000Co-Authors: Chungyang Huang, Kwangting ChengAbstract:We present a new approach to checking assertion properties for RTI, design verification. Our approach combines structural, word-level automatic test pattern generation (ATPG) and modular arithmetic constraint-solving techniques to solve the constraints imposed by the target assertion property. Our word-level ATPG and implication technique not only solves the constraints on the control logic, but also propagates the logic implications to the Datapath. A novel arithmetic constraint solver based on modular number system is then employed to solve the remaining constraints in Datapath. The advantages of the new method are threefold. First, the decision-making process of the word-level ATPG is confined to the selected control signals only. Therefore, the enumeration of enormous number of choices at the Datapath signals is completely avoided. Second, our new implication translation techniques allow word-level logic implication being performed across the boundary of Datapath and control logic, and therefore, efficiently cut down the ATPG search space. Third, our arithmetic constraint solver is based on modular instead of integral number system. It can thus avoid the false negative effect resulting from the bit-vector value modulation. A prototype system has been built which consists of an industrial front-end HDL parser, a property-to-constraint converter and the ATPG/arithmetic constraint-solving engine. The experimental results on some public benchmark and industrial circuits demonstrate the efficiency of our approach and its applicability to large industrial designs.
