The Experts below are selected from a list of 86232 Experts worldwide ranked by ideXlab platform
Jason Cong - One of the best experts on this subject based on the ideXlab platform.
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optimality study of logic synthesis for lut based fpgas
Field Programmable Gate Arrays, 2006Co-Authors: Jason Cong, Kirill MinkovichAbstract:FPGA logic synthesis and Technology Mapping have been studied extensively over the past 15 years. However, progress within the last few years has slowed considerably (with some notable exceptions). It seems natural to then question whether the current logic synthesis and Technology Mapping algorithms for FPGA designs are producing near-optimal solutions. Although there are many empirical studies that compare different FPGA synthesis/Mapping algorithms, little is known about how far these algorithms are from the optimal (recall that both logic optimization and Technology Mapping problems are NP-hard if we consider area optimization in addition to delay/depth optimization). In this paper we present a novel method for constructing arbitrarily large circuits that have known optimal solutions after Technology Mapping. Using these circuits and their derivatives (called LEKO and LEKU, respectively), we show that although leading FPGA Technology Mapping algorithms can produce close to optimal solutions, the results from the entire logic synthesis flow (logic optimization + Mapping) are far from optimal. The best industrial and academic FPGA synthesis flows are around 140 times larger in terms of area on average, and in some cases as much as 500 times larger on LEKU examples. These results clearly indicate that there is much room for further research and improvement in FPGA synthesis.
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FPGA Design Automation: A Survey
Foundations and Trends® in Electronic Design Automation, 2006Co-Authors: Deming Chen, Jason Cong, Peichen PanAbstract:Design automation or computer-aided design (CAD) for field programmable gate arrays (FPGAs) has played a critical role in the rapid advancement and adoption of FPGA Technology over the past two decades. The purpose of this paper is to meet the demand for an up-to-date comprehensive survey/tutorial for FPGA design automation, with an emphasis on the recent developments within the past 5-10 years. The paper focuses on the theory and techniques that have been, or most likely will be, reduced to practice. It covers all major steps in FPGA design flow which includes: routing and placement, circuit clustering, Technology Mapping and architecture-specific optimization, physical synthesis, RT-level and behavior-level synthesis, and power optimization. We hope that this paper can be used both as a guide for beginners who are embarking on research in this relatively young yet exciting area, and a useful reference for established researchers in this field.
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Protecting Combinational Logic Synthesis Solutions
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006Co-Authors: Darko Kirovski, Yean-yow Hwang, Miodrag Potkonjak, Jason CongAbstract:Recently, design reuse has emerged as a dominant design and system-integration paradigm for modern systems on silicon. However, the intellectual-property-business model is vulnerable to many dangerous obstructions, such as misappropriation and copyright fraud. The authors propose a new method for intellectual-property protection that relies upon design watermarking at the combinational-logic-synthesis level. They introduce two protocols for embedding user- and tool-specific information into a logic network while performing multilevel logic minimization and Technology Mapping, two standard-optimization processes during logic synthesis. The hidden information can be used to protect both the design and the synthesis tool. The authors demonstrate that the difficulty of erasing or finding a valid signature in the synthesized design can be made arbitrarily computationally difficult. In order to evaluate the developed-watermarking method, the authors applied it to a standard set of real-life benchmarks, where high probability of authorship was achieved with negligible overhead on solution quality
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daomap a depth optimal area optimization Mapping algorithm for fpga designs
International Conference on Computer Aided Design, 2004Co-Authors: Deming Chen, Jason CongAbstract:In This work we study the Technology Mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chip performance constraint. This is a well-studied topic and a very difficult task (NP-hard). The contributions of This work are as follows: (i) we consider the potential node duplications during the cut enumeration/generation procedure so the Mapping costs encoded in the cuts drive the area-optimization objective more effectively; (ii) after the timing constraint is determined, we will relax the non-critical paths by searching the solution space considering both local and global optimality information to minimize Mapping area; (iii) an iterative cut selection procedure is carried out that further explores and perturbs the solution space to improve solution quality. We guarantee optimal Mapping depth under the unit delay model. Experimental results show that our Mapping algorithm, named DAOmap, produces significant quality and runtime improvements. Compared to the state-of-the-art depth-optimal, area minimization Mapping algorithm CutMap (Cong and Hwan, 1995), DAOmap is 16.02% better on area and runs 24.2X faster on average when both algorithms are Mapping to FPGAs using LUTs of five inputs. LUTs of other inputs are also used for comparisons.
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register binding and port assignment for multiplexer optimization
Asia and South Pacific Design Automation Conference, 2004Co-Authors: Deming Chen, Jason CongAbstract:Data path connection elements, such as multiplexers, consume a significant amount of area on a VLSI chip, especially for FPGA designs. Multiplexer optimization is a difficult problem because both register binding and port assignment to reduce total multiplexer connectivity during high-level synthesis are NP-complete problems. In this paper, we first formulate a k-cofamily-based register binding algorithm targeting the multiplexer optimization problem. We then further reduce the multiplexer width through an efficient port assignment algorithm. Experimental results show that we are 44% better overall than the left-edge register binding algorithm on the total usage of multiplexer inputs and 7% better than a bipartite graph-based algorithm. For large designs, we are able to achieve significantly better results consistently. After Technology Mapping, placement and routing for an FPGA architecture, it shows considerably positive impacts on chip area, delay and power consumption.
Massoud Pedram - One of the best experts on this subject based on the ideXlab platform.
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a dynamic programming based path balancing Technology Mapping algorithm targeting area minimization
International Conference on Computer Aided Design, 2019Co-Authors: Ghasem Pasandi, Massoud PedramAbstract:Path balancing Technology Mapping is a method of Mapping a Technology-independent logical description of a circuit, such as a Boolean network, into a Technology-dependent, gate-level netlist. For a gate-level netlist generated by the path balancing mapper, the difference between lengths of the longest and the shortest paths in the circuit is minimized. To achieve full path balancing, it may be necessary to add buffers on signal paths, and in such a case, the cost of buffers must be properly accounted for. This paper presents a dynamic programming-based Technology Mapping algorithm that generates a minimum-area Mapping solution which is guaranteed to be fully path balanced. The fully path balanced Mapping solution is essential to conventional superconductive single flux quantum circuits, which will fail otherwise. The balanced Mapping solution is also useful in CMOS circuits to avoid (or minimize) unwanted hazard activity and the resulting wasteful dynamic power dissipation as well as to achieve the maximum throughput in a wave-pipelined circuit. Experimental results show that our path balancing Technology Mapping algorithm decreases total area, static power consumption, and path balancing overhead of single flux quantum circuits by large factors. For example, it reduces the circuit area by up to 111% and by an average of 26.3% compared to state-of-the-art Technology mappers.
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pbmap a path balancing Technology Mapping algorithm for single flux quantum logic circuits
IEEE Transactions on Applied Superconductivity, 2019Co-Authors: Ghasem Pasandi, Massoud PedramAbstract:This paper presents a path balancing Technology Mapping algorithm, which is a new algorithm for generating a Mapping solution for a given Boolean network such that the average logic level difference among fanin gates of each gate in the network is minimized. Path balancing Technology Mapping is required in dc-biased single flux quantum (SFQ) circuits for guaranteeing the correct operation, and it is beneficial in CMOS circuits to reduce the hazard issues. We present a dynamic programming based algorithm for path balancing Technology Mapping, which generates optimal solutions for dc-biased SFQ (e.g., rapid SFQ or RSFQ) circuits with tree structure and acts as an effective heuristic for circuits with general directed acyclic graph structure. Experimental results show that our path balancing Technology mapper reduces the balancing overhead by up to 2.7 × and with an average of 21% compared to the state-of-the-art academic Technology mappers.
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sfqmap a Technology Mapping tool for single flux quantum logic circuits
arXiv: Emerging Technologies, 2019Co-Authors: Ghasem Pasandi, Alireza Shafaei, Massoud PedramAbstract:Single flux quantum (SFQ) logic is a promising candidate to replace the CMOS logic for high speed and low power applications due to its superiority in providing high performance and energy efficient circuits. However, developing effective Electronic Design Automation (EDA) tools, which cater to special characteristics and requirements of SFQ circuits such as depth minimization and path balancing, are essential to automate the whole process of designing large SFQ circuits. In this paper, a novel Technology Mapping tool, called SFQmap, is presented, which provides optimization methods for minimizing first the circuit depth and path balancing overhead and then the worst-case stage delay of mapped SFQ circuits. Compared with the state-of-the-art Technology mappers, SFQmap reduces the depth and path balancing overhead by an average of 14% and 31%, respectively.
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pbmap a path balancing Technology Mapping algorithm for single flux quantum logic circuits
arXiv: Emerging Technologies, 2018Co-Authors: Ghasem Pasandi, Massoud PedramAbstract:This paper presents a path balancing Technology Mapping algorithm, which is a new algorithm for generating a Mapping solution for a given Boolean network such that the average logic level difference among fanin gates of each gate in the network is minimized. Path balancing Technology Mapping is required in dc-biased Single Flux Quantum (SFQ) circuits for guaranteeing the correct operation, and it is beneficial in CMOS circuits to reduce the hazard issues. We present a dynamic programming based algorithm for path balancing Technology Mapping which generates optimal solutions for dc-biased SFQ (e.g. Rapid SFQ or RSFQ) circuits with tree structure and acts as an effective heuristic for circuits with general Directed Acyclic Graph (DAG) structure. Experimental results show that our path balancing Technology mapper reduces the balancing overhead by up to 2.7 times and with an average of 21% compared to the state-of-the-art academic Technology mappers.
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Multi-objective optimization techniques for VLSI circuits
Quality Electronic Design (ISQED) 2011 12th International Symposium on, 2011Co-Authors: Fatemeh Kashfi, Sepehr Hatami, Massoud PedramAbstract:The EDA design flows must be retooled to cope with the rapid increase in the number of operational modes and process corners for a VLSI circuit, which in turn results in different and sometimes conflicting design goals and requirements. Single-objective solutions to various design optimization problems, ranging from sizing and fanout optimization to Technology Mapping and cell placement, must hence be augmented to deal with this changing landscape. This paper starts off by presenting a variety of methods for providing analytical models for power and delay to be used in the optimization algorithms. The modeling includes non-convex and convex functional forms. Next, a class of robust and scalable methods for solving multi-objective optimization problems (MOP) in a digital circuit is presented. We present the results of a multi-objective (i.e., power dissipation and delay) gate (transistor) sizing optimization algorithm to demonstrate the effectiveness of our method. We set up the problem as a simultaneous, multi-objective optimization problem and solve it by using the Weighted Sum and Compromise Programming methods. After comparing these two methods, we present the Satisficing Trade-off Method (STOM) to find the most desirable operating point of a circuit.
Deming Chen - One of the best experts on this subject based on the ideXlab platform.
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fast and effective placement and routing directed high level synthesis for fpgas
Field Programmable Gate Arrays, 2014Co-Authors: Hongbin Zheng, Swathi Gurumani, Kyle Rupnow, Deming ChenAbstract:Achievable frequency (fmax) is a widely used input constraint for designs targeting Field-Programmable Gate Arrays (FPGA), because of its impact on design latency and throughput. Fmax is limited by critical path delay, which is highly influenced by lower-level details of the circuit implementation such as Technology Mapping, placement and routing. However, for high-level synthesis~(HLS) design flows, it is challenging to evaluate the real critical delay at the behavioral level. Current HLS flows typically use module pre-characterization for delay estimates. However, we will demonstrate that such delay estimates are not sufficient to obtain high fmax and also minimize total execution latency. In this paper, we introduce a new HLS flow that integrates with Altera's Quartus synthesis and fast placement and routing (PAR) tool to obtain realistic post-PAR delay estimates. This integration enables an iterative flow that improves the performance of the design with both behavioral-level and circuit-level optimizations using realistic delay information. We demonstrate our HLS flow produces up to 24% (on average 20%) improvement in fmax and upto 22% (on average 20%) improvement in execution latency. Furthermore, results demonstrate that our flow is able to achieve from 65% to 91% of the theoretical fmax on Stratix IV devices (550MHz).
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timing constraint driven Technology Mapping for fpgas considering false paths and multi clock domains
International Conference on Computer Aided Design, 2007Co-Authors: Lei Cheng, Deming Chen, Martin D F Wong, Michael D Hutton, Jason GovigAbstract:Modern FPGA chips contain multiple dedicated clocking networks, because nearly all real designs contain multiple clock domains. In this paper, we present an FPGA Technology Mapping algorithm targeting designs with multi-clock domains such as those containing multi-clocks, multi-cycle paths, and false paths. We use timing constraints to handle these unique clocking issues. We work on timing constraint graphs and process multiple arrival/required times for each node in the gate-level netlist. We also recognize and process constraint conflicts efficiently. Our algorithm produces a mapped circuit with the optimal Mapping depth under timing constraints. To the best of our knowledge, this is the first FPGA Mapping algorithm working with multi-clock domains. Experiments show that our algorithm is able to improve circuit performance by 16.8% on average after placement and routing for a set of benchmarks with multi-cycle paths, comparing to a previously published depth-optimal algorithm that does not consider multi-cycle paths.
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FPGA Design Automation: A Survey
Foundations and Trends® in Electronic Design Automation, 2006Co-Authors: Deming Chen, Jason Cong, Peichen PanAbstract:Design automation or computer-aided design (CAD) for field programmable gate arrays (FPGAs) has played a critical role in the rapid advancement and adoption of FPGA Technology over the past two decades. The purpose of this paper is to meet the demand for an up-to-date comprehensive survey/tutorial for FPGA design automation, with an emphasis on the recent developments within the past 5-10 years. The paper focuses on the theory and techniques that have been, or most likely will be, reduced to practice. It covers all major steps in FPGA design flow which includes: routing and placement, circuit clustering, Technology Mapping and architecture-specific optimization, physical synthesis, RT-level and behavior-level synthesis, and power optimization. We hope that this paper can be used both as a guide for beginners who are embarking on research in this relatively young yet exciting area, and a useful reference for established researchers in this field.
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daomap a depth optimal area optimization Mapping algorithm for fpga designs
International Conference on Computer Aided Design, 2004Co-Authors: Deming Chen, Jason CongAbstract:In This work we study the Technology Mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chip performance constraint. This is a well-studied topic and a very difficult task (NP-hard). The contributions of This work are as follows: (i) we consider the potential node duplications during the cut enumeration/generation procedure so the Mapping costs encoded in the cuts drive the area-optimization objective more effectively; (ii) after the timing constraint is determined, we will relax the non-critical paths by searching the solution space considering both local and global optimality information to minimize Mapping area; (iii) an iterative cut selection procedure is carried out that further explores and perturbs the solution space to improve solution quality. We guarantee optimal Mapping depth under the unit delay model. Experimental results show that our Mapping algorithm, named DAOmap, produces significant quality and runtime improvements. Compared to the state-of-the-art depth-optimal, area minimization Mapping algorithm CutMap (Cong and Hwan, 1995), DAOmap is 16.02% better on area and runs 24.2X faster on average when both algorithms are Mapping to FPGAs using LUTs of five inputs. LUTs of other inputs are also used for comparisons.
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register binding and port assignment for multiplexer optimization
Asia and South Pacific Design Automation Conference, 2004Co-Authors: Deming Chen, Jason CongAbstract:Data path connection elements, such as multiplexers, consume a significant amount of area on a VLSI chip, especially for FPGA designs. Multiplexer optimization is a difficult problem because both register binding and port assignment to reduce total multiplexer connectivity during high-level synthesis are NP-complete problems. In this paper, we first formulate a k-cofamily-based register binding algorithm targeting the multiplexer optimization problem. We then further reduce the multiplexer width through an efficient port assignment algorithm. Experimental results show that we are 44% better overall than the left-edge register binding algorithm on the total usage of multiplexer inputs and 7% better than a bipartite graph-based algorithm. For large designs, we are able to achieve significantly better results consistently. After Technology Mapping, placement and routing for an FPGA architecture, it shows considerably positive impacts on chip area, delay and power consumption.
Yuzheng Ding - One of the best experts on this subject based on the ideXlab platform.
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combinational logic synthesis for lut based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems, 1996Co-Authors: Jason Cong, Yuzheng DingAbstract:The increasing popularity of the field programmable gate-array (FPGA) Technology has generated a great deal of interest in the algorithmic study and tool development for FPGA-specific design automation problems. The most widely used FPGAs are LUT based FPGAs, in which the basic logic element is a K -input one-output lookup-table (LUT) that can implement any Boolean function of up to K variables. This unique feature of the LUT has brought new challenges to logic synthesis and optimization, resulting in many new techniques reported in recent years. This article summarizes the research results on combinational logic synthesis for LUT based FPGAs under a coherent framework. These results were dispersed in various conference proceedings and journals and under various formulations and terminologies. We first present general problem formulations, various optimization objectives and measurements, then focus on a set of commonly used basic concepts and techniques, and finally summarize existing synthesis algorithms and systems. We classify and summarize the basic techniques into two categories, namely, logic optimization and Technology Mapping , and describe the existing algorithms and systems in terms of how they use the classified basic techniques. A comprehensive list of references is compiled in the attached bibliography.
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lut based fpga Technology Mapping under arbitrary net delay models
Computer-Aided Design and Computer Graphics, 1994Co-Authors: Jason Cong, Yuzheng Ding, Kuangchien ChenAbstract:Abstract The field programmable gate-array (FPGA) has become an important Technology in VLSI ASIC designs. Most existing algorithms for performance-driven Technology Mapping for Lookup-table (LUT)-based FPGA designs are based on the unit-delay model. In this paper we study the Technology Mapping problem under arbitrary net-delay models. We show that if the net delay can be determined or estimated before Mapping, the problem can be optimally solved in polynomial time based on efficient network flow computation. We have implemented the algorithm and tested it on a number of MCNC benchmark examples.
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flowmap an optimal Technology Mapping algorithm for delay optimization in lookup table based fpga designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1994Co-Authors: Jason Cong, Yuzheng DingAbstract:The field programmable gate-array (FPGA) has become an important Technology in VLSI ASIC designs. In the past few years, a number of heuristic algorithms have been proposed for Technology Mapping in lookup-table (LUT) based FPGA designs, but none of them guarantees optimal solutions for general Boolean networks and little is known about how far their solutions are away from the optimal ones. This paper presents a theoretical breakthrough which shows that the LUT-based FPGA Technology Mapping problem for depth minimization can be solved optimally in polynomial time. A key step in our algorithm is to compute a minimum height K-feasible cut in a network, which is solved optimally in polynomial time based on network flow computation. Our algorithm also effectively minimizes the number of LUT's by maximizing the volume of each cut and by several post-processing operations. Based on these results, we have implemented an LUT-based FPGA Mapping package called FlowMap. We have tested FlowMap on a large set of benchmark examples and compared it with other LUT-based FPGA Mapping algorithms for delay optimization, including Chortle-d, MIS-pga-delay, and DAG-Map. FlowMap reduces the LUT network depth by up to 7% and reduces the number of LUT's by up to 50% compared to the three previous methods. >
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an optimal Technology Mapping algorithm for delay optimization in lookup table based fpga designs
International Conference on Computer Aided Design, 1992Co-Authors: Jason Cong, Yuzheng DingAbstract:The field programmable gate-array (FPGA) has become an important Technology in VLSI ASIC designs. In the past few years, a number of heuristic algorithms have been proposed for Technology Mapping in lookup-table (LUT) based FPGA designs, but none of them guarantees optimal solutions for general Boolean networks and little is known about how far their solutions are away from the optimal ones. This paper presents a theoretical breakthrough which shows that the LUT-based FPGA Technology Mapping problem for depth minimization can be solved optimally in polynomial time. A key step in our algorithm is to compute a minimum height K-feasible cut in a network, which is solved optimally in polynomial time based on network flow computation. Our algorithm also effectively minimizes the number of LUT's by maximizing the volume of each cut and by several post-processing operations. Based on these results, we have implemented an LUT-based FPGA Mapping package called FlowMap. We have tested FlowMap on a large set of benchmark examples and compared it with other LUT-based FPGA Mapping algorithms for delay optimization, including Chortle-d, MIS-pga-delay, and DAG-Map. FlowMap reduces the LUT network depth by up to 7% and reduces the number of LUT's by up to 50% compared to the three previous methods. >
Ghasem Pasandi - One of the best experts on this subject based on the ideXlab platform.
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a dynamic programming based path balancing Technology Mapping algorithm targeting area minimization
International Conference on Computer Aided Design, 2019Co-Authors: Ghasem Pasandi, Massoud PedramAbstract:Path balancing Technology Mapping is a method of Mapping a Technology-independent logical description of a circuit, such as a Boolean network, into a Technology-dependent, gate-level netlist. For a gate-level netlist generated by the path balancing mapper, the difference between lengths of the longest and the shortest paths in the circuit is minimized. To achieve full path balancing, it may be necessary to add buffers on signal paths, and in such a case, the cost of buffers must be properly accounted for. This paper presents a dynamic programming-based Technology Mapping algorithm that generates a minimum-area Mapping solution which is guaranteed to be fully path balanced. The fully path balanced Mapping solution is essential to conventional superconductive single flux quantum circuits, which will fail otherwise. The balanced Mapping solution is also useful in CMOS circuits to avoid (or minimize) unwanted hazard activity and the resulting wasteful dynamic power dissipation as well as to achieve the maximum throughput in a wave-pipelined circuit. Experimental results show that our path balancing Technology Mapping algorithm decreases total area, static power consumption, and path balancing overhead of single flux quantum circuits by large factors. For example, it reduces the circuit area by up to 111% and by an average of 26.3% compared to state-of-the-art Technology mappers.
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pbmap a path balancing Technology Mapping algorithm for single flux quantum logic circuits
IEEE Transactions on Applied Superconductivity, 2019Co-Authors: Ghasem Pasandi, Massoud PedramAbstract:This paper presents a path balancing Technology Mapping algorithm, which is a new algorithm for generating a Mapping solution for a given Boolean network such that the average logic level difference among fanin gates of each gate in the network is minimized. Path balancing Technology Mapping is required in dc-biased single flux quantum (SFQ) circuits for guaranteeing the correct operation, and it is beneficial in CMOS circuits to reduce the hazard issues. We present a dynamic programming based algorithm for path balancing Technology Mapping, which generates optimal solutions for dc-biased SFQ (e.g., rapid SFQ or RSFQ) circuits with tree structure and acts as an effective heuristic for circuits with general directed acyclic graph structure. Experimental results show that our path balancing Technology mapper reduces the balancing overhead by up to 2.7 × and with an average of 21% compared to the state-of-the-art academic Technology mappers.
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sfqmap a Technology Mapping tool for single flux quantum logic circuits
arXiv: Emerging Technologies, 2019Co-Authors: Ghasem Pasandi, Alireza Shafaei, Massoud PedramAbstract:Single flux quantum (SFQ) logic is a promising candidate to replace the CMOS logic for high speed and low power applications due to its superiority in providing high performance and energy efficient circuits. However, developing effective Electronic Design Automation (EDA) tools, which cater to special characteristics and requirements of SFQ circuits such as depth minimization and path balancing, are essential to automate the whole process of designing large SFQ circuits. In this paper, a novel Technology Mapping tool, called SFQmap, is presented, which provides optimization methods for minimizing first the circuit depth and path balancing overhead and then the worst-case stage delay of mapped SFQ circuits. Compared with the state-of-the-art Technology mappers, SFQmap reduces the depth and path balancing overhead by an average of 14% and 31%, respectively.
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pbmap a path balancing Technology Mapping algorithm for single flux quantum logic circuits
arXiv: Emerging Technologies, 2018Co-Authors: Ghasem Pasandi, Massoud PedramAbstract:This paper presents a path balancing Technology Mapping algorithm, which is a new algorithm for generating a Mapping solution for a given Boolean network such that the average logic level difference among fanin gates of each gate in the network is minimized. Path balancing Technology Mapping is required in dc-biased Single Flux Quantum (SFQ) circuits for guaranteeing the correct operation, and it is beneficial in CMOS circuits to reduce the hazard issues. We present a dynamic programming based algorithm for path balancing Technology Mapping which generates optimal solutions for dc-biased SFQ (e.g. Rapid SFQ or RSFQ) circuits with tree structure and acts as an effective heuristic for circuits with general Directed Acyclic Graph (DAG) structure. Experimental results show that our path balancing Technology mapper reduces the balancing overhead by up to 2.7 times and with an average of 21% compared to the state-of-the-art academic Technology mappers.
