The Experts below are selected from a list of 6996 Experts worldwide ranked by ideXlab platform
D.l. Dill - One of the best experts on this subject based on the ideXlab platform.
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ICCAD - Unifying synchronous/asynchronous state machine synthesis
Proceedings of 1993 International Conference on Computer Aided Design (ICCAD), 1993Co-Authors: D.l. DillAbstract:We present a Design Style and synthesis algorithm that encompasses both asynchronous and synchronous state machines. Our proposed Design Style not only supports generalized "burst-mode" multiple-input change asynchronous Designs, but also allows the automatic synthesis of any synchronous Moore machine using only basic gates (and not state-holding elements). Moreover, the synthesis method covers many circuit Styles in the range between burst-mode and fully synchronous. We can easily specify and synthesize sequential circuits which change state on both rising and falling clock edges, have multiple-phase clocks, etc., and mixed synchronous/asynchronous Designs, subject only to setup and hold-time constraints. To demonstrate the effectiveness of the Design Style and the synthesis tool, we present a modified version of a previously published large practical controller Design - the SCSI data transfer controller reDesigned to improve performance and to eliminate preprocessing circuit for converting "level-sensitive" signals to "edge-sensitive" signals, often a cumbersome manual Design process, by interfacing directly with "level-sensitive" signals.
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Unifying synchronous/asynchronous state machine synthesis
Proceedings of 1993 International Conference on Computer Aided Design (ICCAD), 1993Co-Authors: D.l. DillAbstract:We present a Design Style and synthesis algorithm that encompasses both asynchronous and synchronous state machines. Our proposed Design Style not only supports generalized "burst-mode" multiple-input change asynchronous Designs, but also allows the automatic synthesis of any synchronous Moore machine using only basic gates (and not state-holding elements). Moreover, the synthesis method covers many circuit Styles in the range between burst-mode and fully synchronous. We can easily specify and synthesize sequential circuits which change state on both rising and falling clock edges, have multiple-phase clocks, etc., and mixed synchronous/asynchronous Designs, subject only to setup and hold-time constraints. To demonstrate the effectiveness of the Design Style and the synthesis tool, we present a modified version of a previously published large practical controller Design - the SCSI data transfer controller reDesigned to improve performance and to eliminate preprocessing circuit for converting "level-sensitive" signals to "edge-sensitive" signals, often a cumbersome manual Design process, by interfacing directly with "level-sensitive" signals.
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Synthesis of asynchronous state machines using a local clock
[1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1991Co-Authors: Steven M Nowick, D.l. DillAbstract:A novel, correct Design methodology for asynchronous state-machine controllers is presented. The goal of this work is a Design Style as close to a synchronous one as possible, but with the advantages of an asynchronous method. The implementations realize asynchronous state-machine specifications using standard combinational logic, flow latches as storage elements, and a locally-generated clocking signal that pulses whenever there is a change in state. This Design Style allows multiple input changes which can arrive at arbitrary times. The implementations use a minimal or near-minimal number of states. It also allows arbitrary state encoding and flexibility in logic minimization and gate-level realization, so it can take advantage of systematic CAD optimization techniques.
Pierre Bricaud - One of the best experts on this subject based on the ideXlab platform.
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set top box soc Design methodology at stmicroelectronics
Design Automation and Test in Europe, 2003Co-Authors: Francois Remond, Pierre BricaudAbstract:In this paper we will review how the IP Reuse SoC Design methodology has evolved from its first introduction, heavily based on IP Reuse to a state-of- the-art Design flow based on soft and hard IP block and floorplanning tools. This will be illustrated in one complex SoC present in the broadband communication market today, which is a Set Top Box IC containing a proprietary 64-bits processor and some general-purpose blocks, along with dedicated functions specifically Designed by STMicroelectronics. In order to manage Designs of this complexity, a top-down, block-based Design Style, relying on automatic floorplanning tools will be described. This Design Style is using the classical 'divide-and-conquer' strategy and is thus enabling a concurrent development process, guaranteeing timing convergence and correct chip assembly.
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DATE - Set Top Box SoC Design Methodology at STMicroelectronics
2003 Design Automation and Test in Europe Conference and Exhibition, 2003Co-Authors: Francois Remond, Pierre BricaudAbstract:In this paper we will review how the IP Reuse SoC Design methodology has evolved from its first introduction, heavily based on IP Reuse to a state-of- the-art Design flow based on soft and hard IP block and floorplanning tools. This will be illustrated in one complex SoC present in the broadband communication market today, which is a Set Top Box IC containing a proprietary 64-bits processor and some general-purpose blocks, along with dedicated functions specifically Designed by STMicroelectronics. In order to manage Designs of this complexity, a top-down, block-based Design Style, relying on automatic floorplanning tools will be described. This Design Style is using the classical 'divide-and-conquer' strategy and is thus enabling a concurrent development process, guaranteeing timing convergence and correct chip assembly.
I. Soderquist - One of the best experts on this subject based on the ideXlab platform.
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Globally updated mesochronous Design Style
IEEE Journal of Solid-State Circuits, 2003Co-Authors: I. SoderquistAbstract:In large-scale and high-speed digital systems, global synchronization has frequently been used to protect clocked I/O from data failure due to metastability. Synchronous Design Styles are widely used, easy to grasp and to implement, and also well supported by logic synthesis tools. There are many drawbacks with global synchronization. Most important is the relationship between physical size and maximum clock frequency, which will approach its limit as clock frequency and system size increase simultaneously. The purpose of this proposed Globally Updated Mesochronous (GUM) Design Style is to overcome those drawbacks by identifying all global signal links in the system and adding synchronization circuits to these. System level simplicity, inherited from synchronous Design and its tool support, is retained. In this paper, the GUM Design Style is described, analyzed, and demonstrated. Experimental results from a large-scale high-speed system using three 0.8-μm BiCMOS chips are given. The GUM Design Style is scaleable and suitable for future system-on-chip applications both on and among chips.
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Globally updated mesochronous Design Style (GUM-Design-Style)
Proceedings of the 28th European Solid-State Circuits Conference, 2002Co-Authors: I. SoderquistAbstract:In large-scale and high-speed digital systems, global synchronization has frequently been used to protect clocked I/O from data failure do to metastability. Synchronous Design Style is widely used, easy to grasp and to implement, also well supported by logic synthesis tools. There are many drawbacks with global synchronization. Most important is the relationship between physical size and maximum clock frequency, which will approach its limit as clock frequency and system size increase simultaneously. The purpose of this proposed Globally Updated Mesochronous Design Style (GUM-Design-Style) is to overcome those by identifying and allowing all single and bidirectional high-speed signal links needed, still retaining the simplicity uncomplicated implementation and tool support. In this paper GUM-Design-Style is described, analysed and demonstrated. Experimental results from a large-scale high-speed system using three 0.8 µm BiCMOS chips are given. GUM-Design-Style is scaleable and suitable for future System on Chip (SoC) both on and between chips.
Francois Remond - One of the best experts on this subject based on the ideXlab platform.
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set top box soc Design methodology at stmicroelectronics
Design Automation and Test in Europe, 2003Co-Authors: Francois Remond, Pierre BricaudAbstract:In this paper we will review how the IP Reuse SoC Design methodology has evolved from its first introduction, heavily based on IP Reuse to a state-of- the-art Design flow based on soft and hard IP block and floorplanning tools. This will be illustrated in one complex SoC present in the broadband communication market today, which is a Set Top Box IC containing a proprietary 64-bits processor and some general-purpose blocks, along with dedicated functions specifically Designed by STMicroelectronics. In order to manage Designs of this complexity, a top-down, block-based Design Style, relying on automatic floorplanning tools will be described. This Design Style is using the classical 'divide-and-conquer' strategy and is thus enabling a concurrent development process, guaranteeing timing convergence and correct chip assembly.
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DATE - Set Top Box SoC Design Methodology at STMicroelectronics
2003 Design Automation and Test in Europe Conference and Exhibition, 2003Co-Authors: Francois Remond, Pierre BricaudAbstract:In this paper we will review how the IP Reuse SoC Design methodology has evolved from its first introduction, heavily based on IP Reuse to a state-of- the-art Design flow based on soft and hard IP block and floorplanning tools. This will be illustrated in one complex SoC present in the broadband communication market today, which is a Set Top Box IC containing a proprietary 64-bits processor and some general-purpose blocks, along with dedicated functions specifically Designed by STMicroelectronics. In order to manage Designs of this complexity, a top-down, block-based Design Style, relying on automatic floorplanning tools will be described. This Design Style is using the classical 'divide-and-conquer' strategy and is thus enabling a concurrent development process, guaranteeing timing convergence and correct chip assembly.
Abhijit Asati - One of the best experts on this subject based on the ideXlab platform.
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A High Speed Pipelined Dynamic Circuit Implementation Using Modified TSPC Logic Design Style With Improved Performance
2020Co-Authors: Abhijit AsatiAbstract:The high-speed dynamic True Single Phase Clock (TSPC) logic Design Style offer fully pipelined logic circuits using only one clock signal, which makes clock distribution simple and compact. The conversion of simple logic gates to pipelined TSPC logic gates increases transistor count since standard cell implementation for a logic function uses both N-block as well as P-block to remove transparency between pipelined stages, despite the fact that logic functions are only implemented with N-block. In this paper we present a technique in which a TSPC logic cell are implemented both as cell_N and cell_P cells, where each cell block is performing a logic function along with only one type latching operation. Such an implementation allows a systematic approach for converting un-pipelined circuits to fully pipelined circuits. The alternate cell_N and cell_P behaves as dynamic register and removes transparency between pipelined stages. The appropriate numbers of dynamic registers are used to equalize stage delays for all paths and to remove transparency between pipelined stages. The modified TSPC implementation shows almost 40% to 50% reduction in transistor counts and almost 50% reduction in clock cycles as compared to worst-case standard TSPC implementation. The worst-case standard TSPC implementation assumes that no logic merging is possible with P-block, since input to any cell appears after different cycle delays. The modified TSPC logic circuit implementation preserves all the advantages of standard TSPC logic implementation and in addition offers the reduced circuit complexity due to reduced transistor count per logic cell. The proposed logic Design Style reduces layout area and average power consumption as compared to the standard TSPC pipelined circuit implementation.
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Logic Design Style based NBTI Degradation Study using Verilog
2020Co-Authors: Abhijit AsatiAbstract:Negative Bias Temperature Instability (NBTI) is identified as one of the most critical reliability concerns for nanometer scale digital VLSI integrated circuits. Degradation occurring in threshold voltages of PMOS device is most critical as it decides the lifetime of digital circuits in the deep sub-micron technologies. Research on NBTI is active only within community of the device and reliability physics and leading industrial companies develop their models and tools to handle this effect. In this paper we used a switch level Verilog HDL based circuit modeling which incorporates dynamically growth of NBTI effect in transistor switches and its evolutionary impact on circuit performance with time. The proposed technique of NBTI degradation estimation shows dependence of Vt degradation on the minimum period of applied input vectors when input vectors follow temporal randomness which is ignored in the existing techniques. The circuit model was prepared for a 2-input AND gate Designed using four different CMOS logic Design Styles namely static, transmission gate (TG), domino and true single phase clock (TSPC). The AND gate is described using switch level Verilog code incorporates the model for computing the change in threshold voltage (dVt) of PMOS devices after every NBTI stress phase and recovery phase. NBTI stress can be computed by knowing the time for which particular PMOS remain under negative bias (i.e. Vgs
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An improved high speed fully pipelined 500 MHz 8×8 baugh wooley multiplier Design using 0.6 μm CMOS TSPC logic Design Style
2008 IEEE Region 10 and the Third international Conference on Industrial and Information Systems, 2008Co-Authors: Abhijit AsatiAbstract:The Array multipliers are generally preferred for smaller operand sizes due to their simpler VLSI implementations, in-spite of their linear time complexity. The tree multipliers have time complexity of O (log n) but are unsuitable for VLSI implementation since they require larger total routing length, which may degrade performance. The properties of simpler VLSI implementation can be combined with fully pipelined circuit Design using CMOS TSPC (true single phase clock) logic Design Style to improve throughput of array multipliers. In this paper an improved high speed, fully pipelined 8times8 signed Baugh Wooley multiplier circuit has been Designed and implemented using CMOS TSPC logic in 0.6 mum, N-well CMOS process (SCN_SUBM, lambda=0.3) of MOSIS utilizing optimized TSPC logic cells. The simulation results after parasitic extraction show that the inputs can be applied every clock and it can produce correct output after 17 clock cycles at 500 MHz clock rate. Thus the throughput of 500times106 multiplication per second is achieved using TSPC based fine grain pipelining. By Designing and using novel TSPC full adder cell, our Baugh Wooley multiplier implementation shows large reduction in transistor count, average power and delay as compared to an implementation by Robert Rogenmoser and Qiuting Huang. The total transistor count, average power and maximum instantaneous power are indicated in comparison table.
