The Experts below are selected from a list of 4995 Experts worldwide ranked by ideXlab platform
Henrik Sjöland - One of the best experts on this subject based on the ideXlab platform.
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A 26GHz 22.2DbM Variable Gain Power Amplifier in 28NM FD-SOI CMOS for 5G Antenna Arrays
2018 Asia-Pacific Microwave Conference (APMC), 2018Co-Authors: Christian Elgaard, Eric Westesson, Andreas Axholt, Henrik SjölandAbstract:A 26 GHz power amplifier (PA) targeting millimeter wave 5G mobile systems is presented. The two stage PA, integrated in a complete transmitter in a 28 nm FD-SOI CMOS process, only occupies a die area of 0.144 mm2. It uses stacking of two transistors to handle high voltage swing, and a transformer based power combiner at the output to reduce output load impedance. The first stage, the pre-PA (PPA), has 31 unit cells, that can accurately set the gain from 14.7-33.1 Db. The design has been optimized for device stress to provide function for $> \pmb{10}$ years. Saturated output power and 1 Db Compression Point reach state-of-the-art performance of 20.6/22.2Dbm and 18.8/20.7 Dbm for 1.5/ 1.8 V supply respectively. For 1.5 V supply, PAE is peaking at 22.6 % and AM-PM is below 5 degrees up to the 1 Db Compression Point.
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ISCAS - A fully integrated 26 Dbm linearized RF power amplifier in 65nm CMOS technology
2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015Co-Authors: Waqas Ahmad, Markus Tormanen, Henrik SjölandAbstract:In this paper, design and measurements of a fully integrated power amplifier (PA) are presented. The PA consists of two amplifying chains each having a driver and a power stage. A low loss on chip power combiner combines the outputs from two amplifying chains, and also performs impedance transformation and differential to single-ended conversion. To linearize the PA, the driver stage is biased in class-C, acting as a pre-distorter for the power stage which is biased in class-AB. The linearization scheme is validated by measurements, improving the third order intermodulation distortion (IMD3) by 7Db, output referred 1-Db Compression Point by 4Db, and adjacent channel leakage ratio (ACLR) by 4.5 Db. With a supply voltage of 2.2V, the PA delivers a saturated output power of 26.1 Dbm with a power added efficiency (PAE) of 26.8% at operating frequency of 2.24 GHz. The measured power gain of the PA is 21.8 Db, and the output referred 1-Db Compression Point is 25.4 Dbm. The ACLR1 (5 MHz offset) is better than −33 Dbc while transmitting a 23Dbm WCDMA signal. The circuit is manufactured in a standard 65nm CMOS process and occupies 1mm2 of chip area.
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A class-AB 1.65GHz-2GHz broaDband CMOS medium power amplifier
2005 NORCHIP, 2005Co-Authors: H. Aniktar, Henrik Sjöland, Jan H. Mikkelsen, Torben LarsenAbstract:In this paper a single stage broaDband CMOS RF power amplifier is presented. The power amplifier is fabricated in a 0.25/spl mu/m CMOS process. Measurements with a 2.5 V supply voltage show an output power of 18.5 Dbm with an associated PAE of 16% at the 1-Db Compression Point. The measured gain is 5.1 /spl plusmn/ 0.5 Db from 1.65 to 2 GHz. Simulated and measured results agree reasonably well.
Feng-jung Huang - One of the best experts on this subject based on the ideXlab platform.
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A 0.5-/spl mu/m CMOS T/R switch for 900-MHz wireless applications
IEEE Journal of Solid-State Circuits, 2001Co-Authors: Feng-jung HuangAbstract:A single-pole double-throw transmit/receive switch for 3.0-V applications has been fabricated in a 0.5-/spl mu/m CMOS process. An analysis shows that substrate resistances and source/drain-to-body capacitances must be lowered to decrease insertion loss. The switch exhibits a 0.7-Db insertion loss, a 17-Dbm power 1-Db Compression Point (P/sub 1 Db/), and a 42-Db isolation at 928 MHz. The low insertion loss is achieved by optimizing the transistor widths and bias voltages, by minimizing the substrate resistances, and by dc biasing the transmit and receive nodes, which decreases the capacitances while increasing the power 1-Db Compression Point. The switch has adequate insertion loss, isolation, P/sub 1 Db/, and IP/sub 3/ for a number of 900-MHz ISM band applications requiring a moderate peak transmitter power level (/spl sim/15 Dbm).
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A 900-MHz T/R switch with a 0.8-Db insertion loss implemented in a 0.5-/spl mu/m CMOS process
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044), 1Co-Authors: Feng-jung HuangAbstract:A single-pole, double-throw transmit/receive switch for 3.0-V applications has been fabricated in a 0.5-/spl mu/m CMOS process. The switch exhibits a 0.8-Db insertion loss and a 17-Dbm P/sub 1Db/. The low insertion loss is achieved by optimizing the transistor widths and bias voltages, and by minimizing the substrate resistances, while the high 1 Db Compression Point is achieved by DC biasing the input and output nodes.
Fadi R. Shahroury - One of the best experts on this subject based on the ideXlab platform.
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A 1.2-V Low-Power Full-Band Low-Power UWB Transmitter with Integrated Quadrature Voltage-Controlled Oscillator and RF Amplifier in 130nm CMOS technology -
Jordanian Journal of Computers and Information Technology, 2016Co-Authors: Fadi R. ShahrouryAbstract:This paper presents the design and simulation of a low-power full-band UWB transmitter with on-chip quadrature voltage-controlled oscillator (QVCO) in 130 nm CMOS technology. The proposed transmitter consists of a passive poly-phase filter (PPF), QVCO, quadrature modulator core, and RF power amplifier. The QVCO uses the deferential delay cell architecture with four cascaded stages. The transmitter has the following specs a 15.28 Db average conversion gain with a ripple of ±1Db from 2 GHz to 11 GHz. An average input 1-Db Compression Point (IP1Db) is ‒10 Dbm and the average output 1-Db Compression Point (OP1Db) is 4.35 Dbm. The QVCO achieves a wide frequency range (2-11 GHz) with a ‒80 Dbc/Hz phase noise. In addition, the supply voltage of the proposed transmitter is 1.2 V with power consumption of 77.8 mW.
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ISCAS - The design of integrated 3-GHz to 11-GHz CMOS transmitter for full-band ultra-wideband (UWB) applications
2008 IEEE International Symposium on Circuits and Systems, 2008Co-Authors: Wen-chieh Wang, Chang-ping Liao, Zue-der Huang, Fadi R. ShahrouryAbstract:The CMOS integrated 3-GHz to 11-GHz transmitter for full-band UWB applications is proposed and designed in 0.13-mum CMOS technology. The designed UWB transmitter is integrated with a 2:1 frequency divider, a quadrature up-conversion mixer, a balanced RF amplifier, and a 3-stage cascaded poly-phase filter. The technique of inductance peaking has been adopted to achieve 14 -band operation for UWB applications. The transmitter has an average conversion gain of 12.8 Db with the gain ripple of around plusmn1.4 Db among the whole frequency band. The average input 1-Db Compression Point (IP-1Db) of the 14 bands is -12.2 Dbm and the average output 1-Db Compression Point (OP-1Db) of the 14 bands is -0.4 Dbm. The transmitter dissipates the power of 53.1 mW from the supply voltage of 1.2 V and occupies the chip area of 1930times1635 mum2. This chip is designed in 0.13-mum 1P8M CMOS technology and under fabrication.
Maki Soma - One of the best experts on this subject based on the ideXlab platform.
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VTS - RF front-end system gain and linearity built-in test
24th IEEE VLSI Test Symposium, 2006Co-Authors: Qi Wang, Maki SomaAbstract:This work addresses the concurrent on-chip measurement of the gain, the input 1-Db Compression Point (ICP/sub 1-Db/), and the input-referred third-order interference Point (IIP/sub 3/) of individual RF building blocks in RF front-end systems, using introduced high speed CMOS RF on-chip amplitude detectors, which work up to 20 GHz with high accuracy, small area, and low power consumption.
Claudio Turchetti - One of the best experts on this subject based on the ideXlab platform.
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ISCAS (1) - Design of a 4.4 to 5 GHz LNA in 0.25-/spl mu/m SiGe BiCMOS technology
Proceedings of the 2003 International Symposium on Circuits and Systems 2003. ISCAS '03., 1Co-Authors: Paolo Crippa, Simone Orcioni, F. Ricciardi, Claudio TurchettiAbstract:This paper describes a low-noise amplifier (LNA), designed using a 0.25 /spl mu/m SiGe process, operating in the 4.45 GHz band. A power gain of 12.8 Db at 5 GHz has been achieved with a power consumption of 23.77 mW using a 2 V power supply. The noise figure is 2.2 Db while the input referred 1 Db Compression Point is -6.2 Dbm.