The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
Kuopin Chang - One of the best experts on this subject based on the ideXlab platform.
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a novel double density single gate vertical channel sgvc 3d nand flash that is tolerant to deep vertical etching cd variation and possesses robust read disturb immunity
International Electron Devices Meeting, 2015Co-Authors: Chenjun Wu, Kuopin Chang, Yihsuan Hsiao, Chihchang Hsieh, Weichen Chen, Peiying Du, Yuwei Jiang, Roger Lo, Yanru Su, Chiatze HuangAbstract:We demonstrate a novel vertical channel 3D NAND Flash architecture — SGVC. SGVC device is a single-gate, flat-channel TFT charge-trapping device with ultra-thin body. Our novel array Decoding Method enables a tight-pitch (25nm HP) metal BL design to fulfill the large page size (16KB for one plane) for high-performance NAND product. The SGVC flat cell possesses excellent P/E window of ∼10V, small X/Y/Z adjacent-cell interferences, good self-boosting inhibit, and >10K P/E cycling endurance. Due to the advantage of flat cell that is insensitive to etching CD, SGVC device is tolerant to the non-ideal vertical etching and has shown excellent device uniformity from layer to layer. In sharp contract to GAA VC, SGVC suffers no penalty from field-enhancement effect, thus has shown very robust read-disturb immunity against long-term gate stressing. Due to (1) two physical bits per X-Y cell footprint, and (2) efficient array design with minimal overhead, SGVC architecture has 2 to 4 times memory density than GAA VC 3D NAND at the same stacking layer number.
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design innovations to optimize the 3d stackable vertical gate vg nand flash
International Electron Devices Meeting, 2012Co-Authors: Chunhsiung Hung, Kuopin Chang, Yihsuan Hsiao, Chihchang Hsieh, Shuonan Hung, Tiwen Chen, Shihlin Huang, Tzung Shen Chen, Chihshen Chang, Chiehfang ChenAbstract:The design architecture for 3D vertical gate (VG) NAND Flash is discussed in detail. With the unique structure of 3D VG and its Decoding Method, we have developed several important design innovations to optimize this technology: (1) “Shift-BL scramble” to average the BL capacitances, providing uniform C BL 's for various memory layers; (2) Optimized read waveforms to suppress the hot-carrier induced read disturb in the page reading mode; (3) Novel reverse read with “multi-Vt sensing technique” for different memory layers to compensate the Vt variation due to the layer-to-layer process difference; (4) Program inhibit Method and technique to minimize the “Z-directional” self-boosting program disturb in 3D stackable memory. Optimized chip-level performances with excellent memory window for SLC and MLC operations are demonstrated on a 2-layer 3D VG NAND chip.
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a highly pitch scalable 3d vertical gate vg nand flash decoded by a novel self aligned independently controlled double gate idg string select transistor ssl
Symposium on VLSI Technology, 2012Co-Authors: Chihping Chen, Kuopin Chang, Yihsuan Hsiao, Chihchang Hsieh, Yenhao Shih, Tahone Yang, Kuangchao Chen, Shihhung Chen, Kuangyeu Hsieh, Chihyuan LuAbstract:Despite vertical stacking, the lateral scaling of 3D NAND Flash is critically important because otherwise >16 stacking layers are needed to be cost competitive to 20nm 2D NAND. In this work, we propose a 3D vertical gate (VG) NAND using a self-aligned independently controlled double gate (IDG) string select transistor (SSL) Decoding Method. The IDG SSL provides excellent program inhibit and read selection without any penalty of cell size increase, making our 3D VG NAND cell as scalable as conventional 2D NAND. We present the world's first < 50nm (37.5nm) half-pitch 3D NAND. The BL Decoding and page operation Methods are illustrated in detail. This highly pitch scalable VG with IDG SSL approach provides a very cost competitive 3D NAND.
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memory architecture of 3d vertical gate 3dvg nand flash using plural island gate ssl Decoding Method and study of it s program inhibit characteristics
International Memory Workshop, 2012Co-Authors: Kuopin Chang, Hangting Lue, Chihping Chen, Chiehfang Chen, Yanru Chen, Yihsuan Hsiao, Chihchang Hsieh, Yenhao Shih, Tahone Yang, Kuangchao ChenAbstract:The memory architecture of 3D vertical gate (3DVG) NAND Flash using plural island-gate SSL Decoding Method is discussed in detail. In order to provide a good array efficiency, 3DVG shares the wordlines (WL) in vertical direction, and BL's in lateral direction. In order to correctly decode the array, every channel BL has its own island-gate SSL device for the control. Meanwhile, many channel BL's are grouped together in one unit, and the staircase BL contacts are formed in order to decode various memory layers. Page operation is naturally defined by the selection of each island-gate SSL device. Due to the plural SSL devices, the 3DVG architecture inevitably has more pages when stacked layer number is increased, thus program inhibit stress is much larger than conventional 2D NAND. In this work, the program inhibit performances of 3DVG TFT NAND are discussed. Scaling capability down to 3Xnm node is also demonstrated.
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a highly scalable vertical gate vg 3d nand flash with robust program disturb immunity using a novel pn diode Decoding structure
Symposium on VLSI Technology, 2011Co-Authors: Chunhsiung Hung, Kuopin Chang, Chihping Chen, Yihsuan Hsiao, Yenhao Shih, Shihhung Chen, Kuangyeu Hsieh, Mars Yang, Szuyu Wang, Tahone YangAbstract:A novel PN diode Decoding Method for 3D NAND Flash is proposed. The PN diodes are fabricated self-aligned at the source side of the Vertical Gate (VG) 3D NAND architecture. Contrary to the previous 3D NAND approaches, there is no need to fabricate plural string select (SSL) transistors inside the array, thus enabling a highly symmetrical and scalable cell structure. A novel three-step programming pulse waveform is integrated to implement the program-inhibit Method, capitalizing on that the PN diodes can prevent leakage of the self-boosted channel potential. A large program-disturb-free window >5V is demonstrated.
Yihsuan Hsiao - One of the best experts on this subject based on the ideXlab platform.
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a novel double density single gate vertical channel sgvc 3d nand flash that is tolerant to deep vertical etching cd variation and possesses robust read disturb immunity
International Electron Devices Meeting, 2015Co-Authors: Chenjun Wu, Kuopin Chang, Yihsuan Hsiao, Chihchang Hsieh, Weichen Chen, Peiying Du, Yuwei Jiang, Roger Lo, Yanru Su, Chiatze HuangAbstract:We demonstrate a novel vertical channel 3D NAND Flash architecture — SGVC. SGVC device is a single-gate, flat-channel TFT charge-trapping device with ultra-thin body. Our novel array Decoding Method enables a tight-pitch (25nm HP) metal BL design to fulfill the large page size (16KB for one plane) for high-performance NAND product. The SGVC flat cell possesses excellent P/E window of ∼10V, small X/Y/Z adjacent-cell interferences, good self-boosting inhibit, and >10K P/E cycling endurance. Due to the advantage of flat cell that is insensitive to etching CD, SGVC device is tolerant to the non-ideal vertical etching and has shown excellent device uniformity from layer to layer. In sharp contract to GAA VC, SGVC suffers no penalty from field-enhancement effect, thus has shown very robust read-disturb immunity against long-term gate stressing. Due to (1) two physical bits per X-Y cell footprint, and (2) efficient array design with minimal overhead, SGVC architecture has 2 to 4 times memory density than GAA VC 3D NAND at the same stacking layer number.
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design innovations to optimize the 3d stackable vertical gate vg nand flash
International Electron Devices Meeting, 2012Co-Authors: Chunhsiung Hung, Kuopin Chang, Yihsuan Hsiao, Chihchang Hsieh, Shuonan Hung, Tiwen Chen, Shihlin Huang, Tzung Shen Chen, Chihshen Chang, Chiehfang ChenAbstract:The design architecture for 3D vertical gate (VG) NAND Flash is discussed in detail. With the unique structure of 3D VG and its Decoding Method, we have developed several important design innovations to optimize this technology: (1) “Shift-BL scramble” to average the BL capacitances, providing uniform C BL 's for various memory layers; (2) Optimized read waveforms to suppress the hot-carrier induced read disturb in the page reading mode; (3) Novel reverse read with “multi-Vt sensing technique” for different memory layers to compensate the Vt variation due to the layer-to-layer process difference; (4) Program inhibit Method and technique to minimize the “Z-directional” self-boosting program disturb in 3D stackable memory. Optimized chip-level performances with excellent memory window for SLC and MLC operations are demonstrated on a 2-layer 3D VG NAND chip.
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a highly pitch scalable 3d vertical gate vg nand flash decoded by a novel self aligned independently controlled double gate idg string select transistor ssl
Symposium on VLSI Technology, 2012Co-Authors: Chihping Chen, Kuopin Chang, Yihsuan Hsiao, Chihchang Hsieh, Yenhao Shih, Tahone Yang, Kuangchao Chen, Shihhung Chen, Kuangyeu Hsieh, Chihyuan LuAbstract:Despite vertical stacking, the lateral scaling of 3D NAND Flash is critically important because otherwise >16 stacking layers are needed to be cost competitive to 20nm 2D NAND. In this work, we propose a 3D vertical gate (VG) NAND using a self-aligned independently controlled double gate (IDG) string select transistor (SSL) Decoding Method. The IDG SSL provides excellent program inhibit and read selection without any penalty of cell size increase, making our 3D VG NAND cell as scalable as conventional 2D NAND. We present the world's first < 50nm (37.5nm) half-pitch 3D NAND. The BL Decoding and page operation Methods are illustrated in detail. This highly pitch scalable VG with IDG SSL approach provides a very cost competitive 3D NAND.
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memory architecture of 3d vertical gate 3dvg nand flash using plural island gate ssl Decoding Method and study of it s program inhibit characteristics
International Memory Workshop, 2012Co-Authors: Kuopin Chang, Hangting Lue, Chihping Chen, Chiehfang Chen, Yanru Chen, Yihsuan Hsiao, Chihchang Hsieh, Yenhao Shih, Tahone Yang, Kuangchao ChenAbstract:The memory architecture of 3D vertical gate (3DVG) NAND Flash using plural island-gate SSL Decoding Method is discussed in detail. In order to provide a good array efficiency, 3DVG shares the wordlines (WL) in vertical direction, and BL's in lateral direction. In order to correctly decode the array, every channel BL has its own island-gate SSL device for the control. Meanwhile, many channel BL's are grouped together in one unit, and the staircase BL contacts are formed in order to decode various memory layers. Page operation is naturally defined by the selection of each island-gate SSL device. Due to the plural SSL devices, the 3DVG architecture inevitably has more pages when stacked layer number is increased, thus program inhibit stress is much larger than conventional 2D NAND. In this work, the program inhibit performances of 3DVG TFT NAND are discussed. Scaling capability down to 3Xnm node is also demonstrated.
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a highly scalable vertical gate vg 3d nand flash with robust program disturb immunity using a novel pn diode Decoding structure
Symposium on VLSI Technology, 2011Co-Authors: Chunhsiung Hung, Kuopin Chang, Chihping Chen, Yihsuan Hsiao, Yenhao Shih, Shihhung Chen, Kuangyeu Hsieh, Mars Yang, Szuyu Wang, Tahone YangAbstract:A novel PN diode Decoding Method for 3D NAND Flash is proposed. The PN diodes are fabricated self-aligned at the source side of the Vertical Gate (VG) 3D NAND architecture. Contrary to the previous 3D NAND approaches, there is no need to fabricate plural string select (SSL) transistors inside the array, thus enabling a highly symmetrical and scalable cell structure. A novel three-step programming pulse waveform is integrated to implement the program-inhibit Method, capitalizing on that the PN diodes can prevent leakage of the self-boosted channel potential. A large program-disturb-free window >5V is demonstrated.
Chiwai Chow - One of the best experts on this subject based on the ideXlab platform.
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color filter free spatial visible light communication using rgb led and mobile phone camera
Optics Express, 2014Co-Authors: Shih Hao Chen, Chiwai ChowAbstract:A novel color-filter-free visible-light communication (VLC) system using red-green-blue (RGB) light emitting diode (LED) and mobile-phone camera is proposed and demonstrated for the first time. A feature matching Method, which is based on the scale-invariant feature transform (SIFT) algorithm for the received grayscale image is used instead of the chromatic information Decoding Method. The proposed Method is simple and saves the computation complexity. The signal processing is based on the grayscale image computation; hence neither color-filter nor chromatic channel information is required. A proof-of-concept experiment is performed and high performance channel recognition is achieved.
Sunghwan Kim - One of the best experts on this subject based on the ideXlab platform.
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bit level soft run length limited Decoding algorithm for visible light communication
IEEE Photonics Technology Letters, 2016Co-Authors: He Wang, Sunghwan KimAbstract:In this letter, we proposed a bit-level soft (BLS) run-length limited (RLL) Decoding algorithm for visible light communication (VLC). Conventional RLL encoding is only used for dimming control, and the lack of effective RLL Decoding is a long-standing issue in VLC systems. Therefore, an RLL Decoding Method that utilizes soft information from the channel to produce BLS output is proposed for enhancing the performance of the system. The BLS RLL decoder is conjugated with a Reed-Solomon decoder that can efficiently utilize bit-level information from RLL Decoding output. The simulation results show that the bit error rate performance of our proposed RLL Decoding provides a significant gain over that of the conventional RLL Decoding and compares favorably with that of the referenced RLL Decoding Methods.
Ling Wang - One of the best experts on this subject based on the ideXlab platform.
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a memetic algorithm with competition for the capacitated green vehicle routing problem
IEEE CAA Journal of Automatica Sinica, 2019Co-Authors: Ling WangAbstract:In this paper, a memetic algorithm with competition ( MAC ) is proposed to solve the capacitated green vehicle routing problem ( CGVRP ). Firstly, the permutation array called traveling salesman problem ( TSP ) route is used to encode the solution, and an effective Decoding Method to construct the CGVRP route is presented accordingly. Secondly, the k-nearest neighbor ( kNN ) based initialization is presented to take use of the location information of the customers. Thirdly, according to the characteristics of the CGVRP, the search operators in the variable neighborhood search ( VNS ) framework and the simulated annealing ( SA ) strategy are executed on the TSP route for all solutions. Moreover, the customer adjustment operator and the alternative fuel station ( AFS ) adjustment operator on the CGVRP route are executed for the elite solutions after competition. In addition, the crossover operator is employed to share information among different solutions. The effect of parameter setting is investigated using the Taguchi Method of design-of-experiment to suggest suitable values. Via numerical tests, it demonstrates the effectiveness of both the competitive search and the Decoding Method. Moreover, extensive comparative results show that the proposed algorithm is more effective and efficient than the existing Methods in solving the CGVRP.
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an effective teaching learning based optimization algorithm for the flexible job shop scheduling problem with fuzzy processing time
Neurocomputing, 2015Co-Authors: Ye Xu, Ling Wang, Shengyao WangAbstract:In this paper, an effective teaching–learning-based optimization algorithm (TLBO) is proposed to solve the flexible job-shop problem with fuzzy processing time (FJSPF). First, a special encoding scheme is used to represent solutions, and a Decoding Method is employed to transfer a solution to a feasible schedule in the fuzzy sense. Second, a bi-phase crossover scheme based on the teaching–learning mechanism and special local search operators are incorporated into the search framework of the TLBO to balance the exploration and exploitation capabilities. Moreover, the influence of the key parameters on the TLBO is investigated using the Taguchi Method. Finally, numerical results based on some benchmark instances and the comparisons with some existing algorithms are provided. The comparative results demonstrate the effectiveness and efficiency of the proposed TLBO algorithm in solving the FJSPF.
