The Experts below are selected from a list of 112803 Experts worldwide ranked by ideXlab platform
Hideo Ohno - One of the best experts on this subject based on the ideXlab platform.
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a nonvolatile associative Memory based context driven search engine using 90 nm cmos mtj hybrid logic in Memory Architecture
IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2014Co-Authors: Hooman Jarollahi, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu, Naoya Onizawa, Vincent Gripon, Noboru Sakimura, Tadahiko Sugibayashi, Warren J GrossAbstract:This paper presents algorithm, Architecture, and fabrication results of a nonvolatile context-driven search engine that reduces energy consumption as well as computational delay compared to classical hardware and software-based approaches. The proposed Architecture stores only associations between items from multiple search fields in the form of binary links, and merges repeated field items to reduce the Memory requirements and accesses. The fabricated chip achieves $13.6\times$ Memory reduction and 89% energy saving compared to a classical field-based approach in hardware, based on content-addressable Memory (CAM). Furthermore, it achieves $8.6\times$ reduced number of clock cycles in performing search operations compared to the CAM, and five orders of magnitude reduced number of clock cycles compared to a fabricated and measured ultra low-power CPU-based counterpart running a classical search algorithm in software. The energy consumption of the proposed Architecture is on average three orders of magnitude smaller than that of a software-based approach. A magnetic tunnel junction (MTJ)-based logic-in-Memory Architecture is presented that allows simple routing and eliminates leakage current in standby using 90 nm CMOS/MTJ-hybrid technologies.
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mtj based nonvolatile logic in Memory circuit future prospects and issues
Design Automation and Test in Europe, 2009Co-Authors: Shoun Matsunaga, Hideo Ohno, Katsuya Miura, Shoji Ikeda, Jun Hayakawa, Tetsuo Endoh, Takahiro HanyuAbstract:Nonvolatile logic-in-Memory Architecture, where nonvolatile Memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced interconnection delay. This paper presents novel nonvolatile logic circuits based on logic-in-Memory Architecture using magnetic tunnel junctions (MTJs) in combination with MOS transistors. Since the MTJ with a spin-injection write capability is only one device that has all the following superior features as large resistance ratio, virtually unlimited endurance, fast read/write accessibility, scalability, complementary MOS (CMOS)-process compatibility, and nonvolatility, it is very suited to implement the MOS/MTJ-hybrid logic circuit with logic-in-Memory Architecture. A concrete nonvolatile logic-in-Memory circuit is designed and fabricated using a 0.18 µm CMOS/MTJ process, and its future prospects and issues are discussed.
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standby power free compact ternary content addressable Memory cell chip using magnetic tunnel junction devices
Applied Physics Express, 2009Co-Authors: Shoun Matsunaga, Katsuya Miura, Shoji Ikeda, Haruhiro Hasegawa, Jun Hayakawa, Tetsuo Endoh, Kimiyuki Hiyama, Atsushi Matsumoto, Hideo OhnoAbstract:A compact ternary content-addressable Memory (TCAM) cell of 3.15 µm2 with a 0.14 µm complementary metal oxide semiconductor process is realized by the use of nonvolatile magnetic tunnel junction (MTJ) devices with spin-injection write. This TCAM cell based on logic-in-Memory Architecture with nonvolatile MTJs needs no standby power, yet allows instant shut-down of the supply voltage without data backup to an external nonvolatile device.
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Fabrication of a nonvolatile full adder based on logic-in-Memory Architecture using magnetic tunnel junctions
Applied Physics Express, 2008Co-Authors: Shoun Matsunaga, Hideo Ohno, Katsuya Miura, Shoji Ikeda, Haruhiro Hasegawa, Jun Hayakawa, Tetsuo Endoh, Takahiro HanyuAbstract:Nonvolatile logic-in-Memory Architecture, where nonvolatile Memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced interconnection delay. We have fabricated a nonvolatile full adder based on logic-in-Memory Architecture using magnetic tunnel junctions (MTJs) in combination with metal oxide semiconductor (MOS) transistors. Magnesium oxide (MgO) barrier MTJs are used to take advantage of their high tunnel magneto-resistance (TMR) ratio and spin-injection write capability. The MOS transistors are fabricated using a 0.18 µm complementary metal oxide semiconductor (CMOS) process. The basic operation of the full adder is confirmed.
Tetsushi Koide - One of the best experts on this subject based on the ideXlab platform.
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associative Memory for nearest hamming distance search based on frequency mapping
IEEE Journal of Solid-state Circuits, 2012Co-Authors: Hans Jurgen Mattausch, Wataru Imafuku, Akio Kawabata, Tania Ansari, Masahiro Yasuda, Tetsushi KoideAbstract:The developed associative-Memory Architecture utilizes a mapping operation of the Hamming distances into frequency space with ring oscillators programmable in discrete frequency steps. As a result fast word-parallel search of the nearest Hamming distance with low power consumption is obtained. Additionally, high robustness against fabrication-related variations of the MOSFET characteristics is achievable by design because the size of the frequency steps is a freely selectable design parameter which can be adjusted to compensate the variation magnitude. A quantitative analysis of within-die variation effects on the reliability of the associative-Memory Architecture is presented and guidelines for the choice of the design parameters at a given magnitude of the variation effects are derived. Feasibility and performance of this associative-Memory Architecture are experimentally evaluated with a VLSI design in 180 nm CMOS technology containing 64 reference patterns each consisting of 256 bits. The fabricated chip is correctly operating down to low supply voltages (Vdd) of 0.7 V. The power dissipation is less than 36.5 mW and 307 μW at supply voltages of 1.8 V (nominal supply) and 0.7 V, respectively. Measured search reliability is found to be in agreement with measured variations of the important design parameters and expectations from the variation analysis. In comparison to previously reported digital associative-Memory designs, the achieved power dissipation is more than 5 times smaller, while the average search speed is only slightly improved. For Vdd = 1.8 V the search time ranges from a minimum of 50 ns at Hamming distance 0 to a maximum of 245 ns for the largest Hamming distance 255.
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compact associative Memory Architecture with fully parallel search capability for the minimum hamming distance
IEEE Journal of Solid-state Circuits, 2002Co-Authors: Hans Jurgen Mattausch, T Gyohten, Yoshihiro Soda, Tetsushi KoideAbstract:An associative-Memory Architecture for a fully parallel minimum Hamming distance search is proposed, which uses digital circuitry for bit comparison and fast analog circuitry for word comparison as well as winner-take-all (WTA) functionality. Following this original approach allows compact and high-performance integration in conventional CMOS technology. First, static encoding of word-comparison results as a current-sink capability reduces word-comparison circuitry to the theoretical minimum, namely, one transistor per bit and one signal line per word. Second, a new WTA principle, which we call self-adapting winner line-up amplification (WLA), regulates the winner row output automatically into the narrow maximum-gain region of a distance amplifier. Third, winner search circuit complexity scales linear with reference-word number and not quadratic as inevitable for digital approaches. Due to static distance encoding and WLA regulation, transient noise and fabrication process variations are largely tolerated. Only relative chip-internal transistor-parameter variations, creating effective mismatch of matched transistors, limit winner search result correctness. Practical feasibility is verified.
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an Architecture for compact associative memories with deca ns nearest match capability up to large distances
International Solid-State Circuits Conference, 2001Co-Authors: Hans Jurgen Mattausch, T Gyohten, Yoshihiro Soda, Tetsushi KoideAbstract:Associative-Memory Architecture for Hamming-distance search, compact implementation, and short nearest-matches times up to large distances are proposed. The main ideas are fast analog word comparison and self-adaptive winner-line-up amplification. An implementation in a 0.6 /spl mu/m 2-poly 3-metal CMOS technology with 32 rows and 128 columns verifies the key concepts. Search time is <38 ns.
Hans Jurgen Mattausch - One of the best experts on this subject based on the ideXlab platform.
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associative Memory for nearest hamming distance search based on frequency mapping
IEEE Journal of Solid-state Circuits, 2012Co-Authors: Hans Jurgen Mattausch, Wataru Imafuku, Akio Kawabata, Tania Ansari, Masahiro Yasuda, Tetsushi KoideAbstract:The developed associative-Memory Architecture utilizes a mapping operation of the Hamming distances into frequency space with ring oscillators programmable in discrete frequency steps. As a result fast word-parallel search of the nearest Hamming distance with low power consumption is obtained. Additionally, high robustness against fabrication-related variations of the MOSFET characteristics is achievable by design because the size of the frequency steps is a freely selectable design parameter which can be adjusted to compensate the variation magnitude. A quantitative analysis of within-die variation effects on the reliability of the associative-Memory Architecture is presented and guidelines for the choice of the design parameters at a given magnitude of the variation effects are derived. Feasibility and performance of this associative-Memory Architecture are experimentally evaluated with a VLSI design in 180 nm CMOS technology containing 64 reference patterns each consisting of 256 bits. The fabricated chip is correctly operating down to low supply voltages (Vdd) of 0.7 V. The power dissipation is less than 36.5 mW and 307 μW at supply voltages of 1.8 V (nominal supply) and 0.7 V, respectively. Measured search reliability is found to be in agreement with measured variations of the important design parameters and expectations from the variation analysis. In comparison to previously reported digital associative-Memory designs, the achieved power dissipation is more than 5 times smaller, while the average search speed is only slightly improved. For Vdd = 1.8 V the search time ranges from a minimum of 50 ns at Hamming distance 0 to a maximum of 245 ns for the largest Hamming distance 255.
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compact associative Memory Architecture with fully parallel search capability for the minimum hamming distance
IEEE Journal of Solid-state Circuits, 2002Co-Authors: Hans Jurgen Mattausch, T Gyohten, Yoshihiro Soda, Tetsushi KoideAbstract:An associative-Memory Architecture for a fully parallel minimum Hamming distance search is proposed, which uses digital circuitry for bit comparison and fast analog circuitry for word comparison as well as winner-take-all (WTA) functionality. Following this original approach allows compact and high-performance integration in conventional CMOS technology. First, static encoding of word-comparison results as a current-sink capability reduces word-comparison circuitry to the theoretical minimum, namely, one transistor per bit and one signal line per word. Second, a new WTA principle, which we call self-adapting winner line-up amplification (WLA), regulates the winner row output automatically into the narrow maximum-gain region of a distance amplifier. Third, winner search circuit complexity scales linear with reference-word number and not quadratic as inevitable for digital approaches. Due to static distance encoding and WLA regulation, transient noise and fabrication process variations are largely tolerated. Only relative chip-internal transistor-parameter variations, creating effective mismatch of matched transistors, limit winner search result correctness. Practical feasibility is verified.
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an Architecture for compact associative memories with deca ns nearest match capability up to large distances
International Solid-State Circuits Conference, 2001Co-Authors: Hans Jurgen Mattausch, T Gyohten, Yoshihiro Soda, Tetsushi KoideAbstract:Associative-Memory Architecture for Hamming-distance search, compact implementation, and short nearest-matches times up to large distances are proposed. The main ideas are fast analog word comparison and self-adaptive winner-line-up amplification. An implementation in a 0.6 /spl mu/m 2-poly 3-metal CMOS technology with 32 rows and 128 columns verifies the key concepts. Search time is <38 ns.
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hierarchical Architecture for area efficient integrated n port memories with latency free multi gigabit per second access bandwidth
Electronics Letters, 1999Co-Authors: Hans Jurgen MattauschAbstract:A two-level hierarchy is exploited for an area-efficient integrated N-port Memory Architecture, based on 1-port Memory cells. The Architecture is applicable to all types of dynamic, static and novolatile Memory. It allows simultaneous read/write access from all ports, with access-rejection probability adjustable to application needs.
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hierarchical n port Memory Architecture based on 1 port Memory cells
European Solid-State Circuits Conference, 1997Co-Authors: Hans Jurgen MattauschAbstract:The new hierarchical N-port Memory Architecture features parallel read/write access with low access conflict probability from all ports, although only 1-port Memory cells are used. A simple, effective circuit is proposed for conflict handling and monitoring. In comparison with conventional implementation of all N ports in each Memory cell, substantial Memory area reductions between 28% (2 ports) and 68% (16 ports) can be realized, while access times are nearly equivalent. The Architecture is a generalization of the previous state of the art and is applicable for all types of dynamic, static and non-volatile Memory.
Sergio Bampi - One of the best experts on this subject based on the ideXlab platform.
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hybrid scratchpad video Memory Architecture for energy efficient parallel hevc
IEEE Transactions on Circuits and Systems for Video Technology, 2019Co-Authors: Felipe Sampaio, Muhammad Shafique, Bruno Zatt, Jorg Henkel, Sergio BampiAbstract:A hybrid scratchpad video Memory (Hy-SVM) for energy-efficient tiles-parallelized high-efficiency video coding (HEVC) is presented here. The key ideas behind the Hy-SVM include: application-specific design and management; combined multiple levels of private and shared memories that jointly exploit intra-tile and inter-tiles data reuse; scratchpad memories (SPMs) as on-chip data storage; SRAM; and STT-RAM hybrid design. We propose a design methodology for the Hy-SVM that leverages application-specific properties to properly define the SPMs parameters. The inter-tiles data reuse potential of parallel HEVC is exploited by our run-time overlap prediction scheme, which identifies the redundant Memory access behavior by analyzing monitored past frames encoding. Based on the predicted overlap characteristics, the Hy-SVM integrates Memory access management units to control the access dynamics to the private/shared SPM levels. Furthermore, adaptive access management units (APMUs) can strongly reduce on-chip energy consumption due to the predicted overlap formation. The experimental results demonstrate the Hy-SVM overall energy savings of 11%–64% (4-tile) and 8%–46% (8-tile) when compared with related works. From the external Memory perspective, the Hy-SVM can improve data reuse, resulting in 14%–59% of off-chip energy consumption (compared with no inter-tiles data reuse scenarios). In addition, our APMU contributes by reducing on-chip energy consumption of the Hy-SVM by 58%, on average. Thus, compared with related works, the Hy-SVM presents the lowest on-chip energy consumption. Moreover, the overhead of implementing our management units insignificantly affects the performance- and energy-efficiency of the Hy-SVM.
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dsvm energy efficient distributed scratchpad video Memory Architecture for the next generation high efficiency video coding
Design Automation and Test in Europe, 2014Co-Authors: Felipe Sampaio, Muhammad Shafique, Bruno Zatt, Sergio Bampi, Jorg HenkelAbstract:An energy-efficient distributed Scratchpad Video Memory Architecture (dSVM) for the next-generation parallel High Efficiency Video Coding is presented. Our dSVM combines private and overlapping (shared) Scratchpad Memories (SPMs) to support data reuse within and across different cores concurrently executing multiple parallel HEVC threads. We developed a statistical method to size and design the organization of the SPMs along with a supporting Memory reading policy for energy efficiency. The key is to leverage the HEVC and video content knowledge. Furthermore, we integrate an adaptive power management policy for SPMs to manage the power states of different Memory parts at run time depending upon the varying video content properties. Our experimental results illustrate that our dSVM Architecture reduces the overall Memory energy consumption by up to 51%-61% compared to parallelized state-of-the-art solutions [11]. The dSVM external Memory energy savings increase with an increasing number of parallel HEVC threads and size of search window. Moreover, our SPM power management reacts to the current video properties and achieves up to 54% on-chip leakage energy savings.
Katsuya Miura - One of the best experts on this subject based on the ideXlab platform.
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mtj based nonvolatile logic in Memory circuit future prospects and issues
Design Automation and Test in Europe, 2009Co-Authors: Shoun Matsunaga, Hideo Ohno, Katsuya Miura, Shoji Ikeda, Jun Hayakawa, Tetsuo Endoh, Takahiro HanyuAbstract:Nonvolatile logic-in-Memory Architecture, where nonvolatile Memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced interconnection delay. This paper presents novel nonvolatile logic circuits based on logic-in-Memory Architecture using magnetic tunnel junctions (MTJs) in combination with MOS transistors. Since the MTJ with a spin-injection write capability is only one device that has all the following superior features as large resistance ratio, virtually unlimited endurance, fast read/write accessibility, scalability, complementary MOS (CMOS)-process compatibility, and nonvolatility, it is very suited to implement the MOS/MTJ-hybrid logic circuit with logic-in-Memory Architecture. A concrete nonvolatile logic-in-Memory circuit is designed and fabricated using a 0.18 µm CMOS/MTJ process, and its future prospects and issues are discussed.
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standby power free compact ternary content addressable Memory cell chip using magnetic tunnel junction devices
Applied Physics Express, 2009Co-Authors: Shoun Matsunaga, Katsuya Miura, Shoji Ikeda, Haruhiro Hasegawa, Jun Hayakawa, Tetsuo Endoh, Kimiyuki Hiyama, Atsushi Matsumoto, Hideo OhnoAbstract:A compact ternary content-addressable Memory (TCAM) cell of 3.15 µm2 with a 0.14 µm complementary metal oxide semiconductor process is realized by the use of nonvolatile magnetic tunnel junction (MTJ) devices with spin-injection write. This TCAM cell based on logic-in-Memory Architecture with nonvolatile MTJs needs no standby power, yet allows instant shut-down of the supply voltage without data backup to an external nonvolatile device.
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Fabrication of a nonvolatile full adder based on logic-in-Memory Architecture using magnetic tunnel junctions
Applied Physics Express, 2008Co-Authors: Shoun Matsunaga, Hideo Ohno, Katsuya Miura, Shoji Ikeda, Haruhiro Hasegawa, Jun Hayakawa, Tetsuo Endoh, Takahiro HanyuAbstract:Nonvolatile logic-in-Memory Architecture, where nonvolatile Memory elements are distributed over a logic-circuit plane, is expected to realize both ultra-low-power and reduced interconnection delay. We have fabricated a nonvolatile full adder based on logic-in-Memory Architecture using magnetic tunnel junctions (MTJs) in combination with metal oxide semiconductor (MOS) transistors. Magnesium oxide (MgO) barrier MTJs are used to take advantage of their high tunnel magneto-resistance (TMR) ratio and spin-injection write capability. The MOS transistors are fabricated using a 0.18 µm complementary metal oxide semiconductor (CMOS) process. The basic operation of the full adder is confirmed.
