The Experts below are selected from a list of 93150 Experts worldwide ranked by ideXlab platform
A Ripp - One of the best experts on this subject based on the ideXlab platform.
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DATE 2006 Special Session: DFM/DFY Design for Manufacturability and Yield - influence of process variations in digital, analog and mixed-signal circuit Design
Proceedings of the Design Automation & Test in Europe Conference, 2006Co-Authors: A Ripp, Markus Buhler, Juergen Koehl, Jeanne P Bickford, Jason D Hibbeler, Ulf Schlichtmann, R Sommer, M PronathAbstract:The concepts of Design for Manufacturability and Design for yield DFM/DFY are bringing together domains that co-existed mostly separated until now $circuit Design, physical Design and manufacturing process. New requirements like SoC, mixed analog/digital Design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deep-submicron technologies is to Design and verify integrated circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the Designed and manufactured circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. for technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. ReDesigns and, therefore, respins of the whole development and manufacturing chain lead to high costs of multiple manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the Design phase of digital, analog, and mixed-signal circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial Design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels - both for digital as well as for analog - is a big challenge. Yield analysis and optimization is currently applied to individual circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results - best/worst case and OCV (on chip variation) factor - for the digital parts. On the other hand for analog often very high efforts are spent to Design individual blocks with high robustness (>6sigma). for abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. for the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices
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dfm dfy Design for Manufacturability and yield influence of process variations in digital analog and mixed signal circuit Design
Design Automation and Test in Europe, 2006Co-Authors: Markus Buhler, Juergen Koehl, Jeanne P Bickford, Jason D Hibbeler, Ulf Schlichtmann, R Sommer, M Pronath, A RippAbstract:The concepts of Design for Manufacturability and Design for Yield DFM/DFY are bringing together domains that co-existed mostly separated until now -- circuit Design, physical Design and manufacturing process. New requirements like SoC, mixed analog/digital Design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deep-submicron technologies is to Design and verify integrated circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the Designed and manufactured circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. for technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. ReDesigns and, therefore, respins of the whole development and manufacturing chain lead to high costs of multiple manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the Design phase of digital, analog, and mixed-signal circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial Design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels -- both for digital as well as for analog is a big challenge. Yield analysis and optimization is currently applied to individual circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results - best/worst case and OCV (On Chip Variation) factor - for the digital parts. On the other hand for analog often very high efforts are spent to Design individual blocks with high robustness (>6σ). for abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. for the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices.
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date 2006 special session dfm dfy Design for Manufacturability and yield influence of process variations in digital analog and mixed signal circuit Design
Design Automation and Test in Europe, 2006Co-Authors: Markus Buhler, Juergen Koehl, Jeanne P Bickford, Jason D Hibbeler, Ulf Schlichtmann, R Sommer, M Pronath, A RippAbstract:The concepts of Design for Manufacturability and Design for yield DFM/DFY are bringing together domains that co-existed mostly separated until now $circuit Design, physical Design and manufacturing process. New requirements like SoC, mixed analog/digital Design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deep-submicron technologies is to Design and verify integrated circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the Designed and manufactured circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. for technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. ReDesigns and, therefore, respins of the whole development and manufacturing chain lead to high costs of multiple manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the Design phase of digital, analog, and mixed-signal circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial Design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels - both for digital as well as for analog - is a big challenge. Yield analysis and optimization is currently applied to individual circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results - best/worst case and OCV (on chip variation) factor - for the digital parts. On the other hand for analog often very high efforts are spent to Design individual blocks with high robustness (>6sigma). for abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. for the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices
Yao-wen Chang - One of the best experts on this subject based on the ideXlab platform.
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recent research and emerging challenges in physical Design for Manufacturability reliability
Asia and South Pacific Design Automation Conference, 2007Co-Authors: Ming-chao Tsai, Tai-chen Chen, Ting-chi Wang, Yao-wen ChangAbstract:As IC process geometries scale down to the nanometer territory, the industry faces severe challenges of manufacturing limitations. To guarantee yield and reliability, physical Design for Manufacturability and reliability has played a pivotal role in resolution and thus yield enhancement for the imperfect manufacturing process. In this paper, we introduce major challenges arising from nanometer process technology, survey key existing techniques for handling the challenges, and provide some future research directions in physical Design for Manufacturability and reliability.
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Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability
2007 Asia and South Pacific Design Automation Conference, 2007Co-Authors: Ming-chao Tsai, Tai-chen Chen, Ting-chi Wang, Yao-wen ChangAbstract:As IC process geometries scale down to the nanometer territory, the industry faces severe challenges of manufacturing limitations. To guarantee yield and reliability, physical Design for Manufacturability and reliability has played a pivotal role in resolution and thus yield enhancement for the imperfect manufacturing process. In this paper, we introduce major challenges arising from nanometer process technology, survey key existing techniques for handling the challenges, and provide some future research directions in physical Design for Manufacturability and reliability.
Markus Buhler - One of the best experts on this subject based on the ideXlab platform.
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DATE 2006 Special Session: DFM/DFY Design for Manufacturability and Yield - influence of process variations in digital, analog and mixed-signal circuit Design
Proceedings of the Design Automation & Test in Europe Conference, 2006Co-Authors: A Ripp, Markus Buhler, Juergen Koehl, Jeanne P Bickford, Jason D Hibbeler, Ulf Schlichtmann, R Sommer, M PronathAbstract:The concepts of Design for Manufacturability and Design for yield DFM/DFY are bringing together domains that co-existed mostly separated until now $circuit Design, physical Design and manufacturing process. New requirements like SoC, mixed analog/digital Design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deep-submicron technologies is to Design and verify integrated circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the Designed and manufactured circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. for technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. ReDesigns and, therefore, respins of the whole development and manufacturing chain lead to high costs of multiple manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the Design phase of digital, analog, and mixed-signal circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial Design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels - both for digital as well as for analog - is a big challenge. Yield analysis and optimization is currently applied to individual circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results - best/worst case and OCV (on chip variation) factor - for the digital parts. On the other hand for analog often very high efforts are spent to Design individual blocks with high robustness (>6sigma). for abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. for the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices
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dfm dfy Design for Manufacturability and yield influence of process variations in digital analog and mixed signal circuit Design
Design Automation and Test in Europe, 2006Co-Authors: Markus Buhler, Juergen Koehl, Jeanne P Bickford, Jason D Hibbeler, Ulf Schlichtmann, R Sommer, M Pronath, A RippAbstract:The concepts of Design for Manufacturability and Design for Yield DFM/DFY are bringing together domains that co-existed mostly separated until now -- circuit Design, physical Design and manufacturing process. New requirements like SoC, mixed analog/digital Design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deep-submicron technologies is to Design and verify integrated circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the Designed and manufactured circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. for technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. ReDesigns and, therefore, respins of the whole development and manufacturing chain lead to high costs of multiple manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the Design phase of digital, analog, and mixed-signal circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial Design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels -- both for digital as well as for analog is a big challenge. Yield analysis and optimization is currently applied to individual circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results - best/worst case and OCV (On Chip Variation) factor - for the digital parts. On the other hand for analog often very high efforts are spent to Design individual blocks with high robustness (>6σ). for abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. for the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices.
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date 2006 special session dfm dfy Design for Manufacturability and yield influence of process variations in digital analog and mixed signal circuit Design
Design Automation and Test in Europe, 2006Co-Authors: Markus Buhler, Juergen Koehl, Jeanne P Bickford, Jason D Hibbeler, Ulf Schlichtmann, R Sommer, M Pronath, A RippAbstract:The concepts of Design for Manufacturability and Design for yield DFM/DFY are bringing together domains that co-existed mostly separated until now $circuit Design, physical Design and manufacturing process. New requirements like SoC, mixed analog/digital Design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deep-submicron technologies is to Design and verify integrated circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the Designed and manufactured circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. for technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. ReDesigns and, therefore, respins of the whole development and manufacturing chain lead to high costs of multiple manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the Design phase of digital, analog, and mixed-signal circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial Design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels - both for digital as well as for analog - is a big challenge. Yield analysis and optimization is currently applied to individual circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results - best/worst case and OCV (on chip variation) factor - for the digital parts. On the other hand for analog often very high efforts are spent to Design individual blocks with high robustness (>6sigma). for abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. for the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices
M Pronath - One of the best experts on this subject based on the ideXlab platform.
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DATE 2006 Special Session: DFM/DFY Design for Manufacturability and Yield - influence of process variations in digital, analog and mixed-signal circuit Design
Proceedings of the Design Automation & Test in Europe Conference, 2006Co-Authors: A Ripp, Markus Buhler, Juergen Koehl, Jeanne P Bickford, Jason D Hibbeler, Ulf Schlichtmann, R Sommer, M PronathAbstract:The concepts of Design for Manufacturability and Design for yield DFM/DFY are bringing together domains that co-existed mostly separated until now $circuit Design, physical Design and manufacturing process. New requirements like SoC, mixed analog/digital Design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deep-submicron technologies is to Design and verify integrated circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the Designed and manufactured circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. for technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. ReDesigns and, therefore, respins of the whole development and manufacturing chain lead to high costs of multiple manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the Design phase of digital, analog, and mixed-signal circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial Design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels - both for digital as well as for analog - is a big challenge. Yield analysis and optimization is currently applied to individual circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results - best/worst case and OCV (on chip variation) factor - for the digital parts. On the other hand for analog often very high efforts are spent to Design individual blocks with high robustness (>6sigma). for abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. for the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices
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dfm dfy Design for Manufacturability and yield influence of process variations in digital analog and mixed signal circuit Design
Design Automation and Test in Europe, 2006Co-Authors: Markus Buhler, Juergen Koehl, Jeanne P Bickford, Jason D Hibbeler, Ulf Schlichtmann, R Sommer, M Pronath, A RippAbstract:The concepts of Design for Manufacturability and Design for Yield DFM/DFY are bringing together domains that co-existed mostly separated until now -- circuit Design, physical Design and manufacturing process. New requirements like SoC, mixed analog/digital Design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deep-submicron technologies is to Design and verify integrated circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the Designed and manufactured circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. for technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. ReDesigns and, therefore, respins of the whole development and manufacturing chain lead to high costs of multiple manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the Design phase of digital, analog, and mixed-signal circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial Design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels -- both for digital as well as for analog is a big challenge. Yield analysis and optimization is currently applied to individual circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results - best/worst case and OCV (On Chip Variation) factor - for the digital parts. On the other hand for analog often very high efforts are spent to Design individual blocks with high robustness (>6σ). for abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. for the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices.
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date 2006 special session dfm dfy Design for Manufacturability and yield influence of process variations in digital analog and mixed signal circuit Design
Design Automation and Test in Europe, 2006Co-Authors: Markus Buhler, Juergen Koehl, Jeanne P Bickford, Jason D Hibbeler, Ulf Schlichtmann, R Sommer, M Pronath, A RippAbstract:The concepts of Design for Manufacturability and Design for yield DFM/DFY are bringing together domains that co-existed mostly separated until now $circuit Design, physical Design and manufacturing process. New requirements like SoC, mixed analog/digital Design and deep-submicron technologies force to a mutual integration of all levels. A major challenge coming with new deep-submicron technologies is to Design and verify integrated circuits for high yield. Random and systematic defects as well as parametric process variations have a large influence on quality and yield of the Designed and manufactured circuits. With further shrinking of process technology, the on-chip variation is getting worse for each technology node. for technologies larger than 180nm feature sizes, variations are mostly in a range of below 10%. Here an acceptable yield range is achieved by regular but error-prone re-shifts of the drifting process. However, shrinking technologies down to 90nm, 65nm and below cause on-chip variations of more than 50%. It is understandable that tuning the technology process alone is not enough to guarantee sufficient yield and robustness levels any more. ReDesigns and, therefore, respins of the whole development and manufacturing chain lead to high costs of multiple manufacturing runs. All together the risk to miss the given market window is extremely high. Thus, it becomes inevitable to have a seamless DFM/DFY concept realized for the Design phase of digital, analog, and mixed-signal circuits. New DFY methodologies are coming up for parametric yield analysis and optimization and have recently been made available for the industrial Design of individual analog blocks on transistor level up to 1500 transistors. The transfer of yield analysis and yield optimization techniques to other abstraction levels - both for digital as well as for analog - is a big challenge. Yield analysis and optimization is currently applied to individual circuit blocks and not to the overall chip yielding on the one hand often too pessimistic results - best/worst case and OCV (on chip variation) factor - for the digital parts. On the other hand for analog often very high efforts are spent to Design individual blocks with high robustness (>6sigma). for abstraction to higher digital levels first approaches like statistical static timing analysis (SSTA) are under development. for the analog parts a strategy to develop macro models and hierarchical simulation or behavioral simulation methodologies is required that includes low-level statistical effects caused by local and global process variation of the individual devices
Ming-chao Tsai - One of the best experts on this subject based on the ideXlab platform.
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recent research and emerging challenges in physical Design for Manufacturability reliability
Asia and South Pacific Design Automation Conference, 2007Co-Authors: Ming-chao Tsai, Tai-chen Chen, Ting-chi Wang, Yao-wen ChangAbstract:As IC process geometries scale down to the nanometer territory, the industry faces severe challenges of manufacturing limitations. To guarantee yield and reliability, physical Design for Manufacturability and reliability has played a pivotal role in resolution and thus yield enhancement for the imperfect manufacturing process. In this paper, we introduce major challenges arising from nanometer process technology, survey key existing techniques for handling the challenges, and provide some future research directions in physical Design for Manufacturability and reliability.
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Recent Research and Emerging Challenges in Physical Design for Manufacturability/Reliability
2007 Asia and South Pacific Design Automation Conference, 2007Co-Authors: Ming-chao Tsai, Tai-chen Chen, Ting-chi Wang, Yao-wen ChangAbstract:As IC process geometries scale down to the nanometer territory, the industry faces severe challenges of manufacturing limitations. To guarantee yield and reliability, physical Design for Manufacturability and reliability has played a pivotal role in resolution and thus yield enhancement for the imperfect manufacturing process. In this paper, we introduce major challenges arising from nanometer process technology, survey key existing techniques for handling the challenges, and provide some future research directions in physical Design for Manufacturability and reliability.
