The Experts below are selected from a list of 34074 Experts worldwide ranked by ideXlab platform

J.-y. Jou - One of the best experts on this subject based on the ideXlab platform.

  • A functional fault model for sequential machines
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
    Co-Authors: Kwang-ting Cheng, J.-y. Jou
    Abstract:

    A fault model at the State transition level is proposed for finite State machines. In this model, a fault causes the Destination State of a State transition to be faulty. Analysis shows that a test set that detects all single-State-transition (SST) faults will also detect most multiple-State-transition (MST) faults in practical finite State machines. The quality of the test set generated for SST faults is close to that of the sequences derived from the checking experiment. It is also shown that the upper bound of the length of the SST fault test is 2MN/sup 2/ for an N-State M-transition machine, while that of the checking sequence is exponential. An automatic test generation algorithm and a test generation system, FTG, based on the model show that the test set generated for SST faults achieves high single stuck-at-fault coverage as well as high transistor fault coverage for multilevel implementations of the machine. >

  • ICCAD - A single-State-transition fault model for sequential machines
    1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers, 1
    Co-Authors: Kwang-ting Cheng, J.-y. Jou
    Abstract:

    A fault model in the State transition level of finite State machines is studied. In this model, called a single-State-transition (SST) fault model, a fault causes a State transition to go to a wrong Destination State while leaving its input/output label intact. An analysis is given to show that a test set that detects all SST faults will also detect most multiple-State-transition (MST) faults in practical finite State machines. It is shown that, for an N-State M-transaction machine, the length of the SST fault test set is upper-bounded by 2*M*N/sup 2/ while the length is exponential in terms of N for a checking experiment. Experimental results show that the test set generated for SST faults achieves not only a high single stuck-at fault coverage but also a high transistor fault coverage for a multilevel implementation of the machine. >

  • ITC - Functional test generation for finite State machines
    Proceedings. International Test Conference 1990, 1
    Co-Authors: Kwang-ting Cheng, J.-y. Jou
    Abstract:

    A functional test generation method for finite-State machines is described. A functional fault model, called the single-transition fault model, on the State transition level is used. In this model, a fault causes a single transition to a wrong Destination State. A fault-collapsing technique for this fault model is also described. For each State transition, a small subset of States is selected as the faulty Destination States so that the number of modeled faults for test generation is minimized. On the basis of this fault model, the authors developed an automatic test generation algorithm and built a test generation system. The effectiveness of this method is shown by experimental results on a set of benchmark finite-State machines. A 100% stuck-at fault coverage is achieved by the proposed method for several machines, and a very high coverage (>97%) is also obtained for other machines. In comparison with a gate-level test generator STG3, the test generation time is speeded up by a factor of 100. >

Kwang-ting Cheng - One of the best experts on this subject based on the ideXlab platform.

  • A functional fault model for sequential machines
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1992
    Co-Authors: Kwang-ting Cheng, J.-y. Jou
    Abstract:

    A fault model at the State transition level is proposed for finite State machines. In this model, a fault causes the Destination State of a State transition to be faulty. Analysis shows that a test set that detects all single-State-transition (SST) faults will also detect most multiple-State-transition (MST) faults in practical finite State machines. The quality of the test set generated for SST faults is close to that of the sequences derived from the checking experiment. It is also shown that the upper bound of the length of the SST fault test is 2MN/sup 2/ for an N-State M-transition machine, while that of the checking sequence is exponential. An automatic test generation algorithm and a test generation system, FTG, based on the model show that the test set generated for SST faults achieves high single stuck-at-fault coverage as well as high transistor fault coverage for multilevel implementations of the machine. >

  • ICCAD - A single-State-transition fault model for sequential machines
    1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers, 1
    Co-Authors: Kwang-ting Cheng, J.-y. Jou
    Abstract:

    A fault model in the State transition level of finite State machines is studied. In this model, called a single-State-transition (SST) fault model, a fault causes a State transition to go to a wrong Destination State while leaving its input/output label intact. An analysis is given to show that a test set that detects all SST faults will also detect most multiple-State-transition (MST) faults in practical finite State machines. It is shown that, for an N-State M-transaction machine, the length of the SST fault test set is upper-bounded by 2*M*N/sup 2/ while the length is exponential in terms of N for a checking experiment. Experimental results show that the test set generated for SST faults achieves not only a high single stuck-at fault coverage but also a high transistor fault coverage for a multilevel implementation of the machine. >

  • ITC - Functional test generation for finite State machines
    Proceedings. International Test Conference 1990, 1
    Co-Authors: Kwang-ting Cheng, J.-y. Jou
    Abstract:

    A functional test generation method for finite-State machines is described. A functional fault model, called the single-transition fault model, on the State transition level is used. In this model, a fault causes a single transition to a wrong Destination State. A fault-collapsing technique for this fault model is also described. For each State transition, a small subset of States is selected as the faulty Destination States so that the number of modeled faults for test generation is minimized. On the basis of this fault model, the authors developed an automatic test generation algorithm and built a test generation system. The effectiveness of this method is shown by experimental results on a set of benchmark finite-State machines. A 100% stuck-at fault coverage is achieved by the proposed method for several machines, and a very high coverage (>97%) is also obtained for other machines. In comparison with a gate-level test generator STG3, the test generation time is speeded up by a factor of 100. >

Dimitri P. Bertsekas - One of the best experts on this subject based on the ideXlab platform.

  • Robust shortest path planning and semicontractive dynamic programming
    Naval Research Logistics (NRL), 2016
    Co-Authors: Dimitri P. Bertsekas
    Abstract:

    In this article, we consider shortest path problems in a directed graph where the transitions between nodes are subject to uncertainty. We use a minimax formulation, where the objective is to guarantee that a special Destination State is reached with a minimum cost path under the worst possible instance of the uncertainty. Problems of this type arise, among others, in planning and pursuit-evasion contexts, and in model predictive control. Our analysis makes use of the recently developed theory of abstract semicontractive dynamic programming models. We investigate questions of existence and uniqueness of solution of the optimality equation, existence of optimal paths, and the validity of various algorithms patterned after the classical methods of value and policy iteration, as well as a Dijkstra-like algorithm for problems with nonnegative arc lengths.© 2016 Wiley Periodicals, Inc. Naval Research Logistics, 2016

  • Robust Shortest Path Planning and Semicontractive Dynamic Programming
    arXiv: Data Structures and Algorithms, 2016
    Co-Authors: Dimitri P. Bertsekas
    Abstract:

    In this paper we consider shortest path problems in a directed graph where the transitions between nodes are subject to uncertainty. We use a minimax formulation, where the objective is to guarantee that a special Destination State is reached with a minimum cost path under the worst possible instance of the uncertainty. Problems of this type arise, among others, in planning and pursuit-evasion contexts, and in model predictive control. Our analysis makes use of the recently developed theory of abstract semicontractive dynamic programming models. We investigate questions of existence and uniqueness of solution of the optimality equation, existence of optimal paths, and the validity of various algorithms patterned after the classical methods of value and policy iteration, as well as a Dijkstra-like algorithm for problems with nonnegative arc lengths.

D.r. Choudhury - One of the best experts on this subject based on the ideXlab platform.

  • Asian Test Symposium - Generation of an ordered sequence of test vectors for single State transition faults in large sequential machines
    Proceedings 10th Asian Test Symposium, 1
    Co-Authors: S. Goswami, A. Chanda, D.r. Choudhury
    Abstract:

    A new strategy for the generation of test vectors for testing large sequential machine has been proposed. The fault model assumed is the single State transition (SST) fault model where a fault corrupts the Destination State of exactly one transition of the machine, the rest of the transitions being unaffected. The strategy takes into consideration the behaviour of the machine under test and generates a set of test vectors. The main contribution of this paper is that it creates an ordering of the test vectors generated, if these test vectors are applied in the same order during testing, it maximizes the fault coverage in the least possible time with high probability. Also this approach reduces the traversal space of the machine under test by eliminating a set of transitions where the chance of detecting an existing fault is poor. The approach also ensures that the test vectors are such that when applied for testing they do not result in the repeated traversal of the same part of the machine. This helps in reducing the time of testing without compromising the extent of fault coverage of the testing procedure.

Diederik Verkest - One of the best experts on this subject based on the ideXlab platform.

  • Concepts and Implementation of Spatial Division Multiplexing for Guaranteed Throughput in Networks-on-Chip
    IEEE Transactions on Computers, 2008
    Co-Authors: Anthony Leroy, Dragomir Milojevic, Diederik Verkest, Frédéric Robert, Francky Catthoor
    Abstract:

    To ensure low power consumption while maintaining flexibility and performance, future systems-on-chip (SoC) will combine several types of processor cores and data memory units of widely different sizes. To interconnect the IPs of these heterogeneous platforms, networks-on-chip (NoC) have been proposed as an efficient and scalable alternative to shared buses. NoCs can provide throughput and latency guarantees by establishing virtual circuits between source and Destination. State-of-the-art NoCs currently exploit time-division multiplexing (TDM) to share network resources among virtual circuits, but this typically results in high network area and energy overhead with long circuit set-up time. We propose an alternative solution based on spatial division multiplexing (SDM). This paper describes our design of an SDM-based network, discusses design alternatives for network implementation and shows why SDM can be better adapted to NoCs than TDM in a specific context. Our case study clearly illustrates the advantages of our technique over TDM in terms of energy consumption, area overhead, and flexibility. A comparison is also performed with a State-of-the-art industrial reference NoC: Arteris.

  • CODES+ISSS - Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs
    Proceedings of the 3rd IEEE ACM IFIP international conference on Hardware software codesign and system synthesis - CODES+ISSS '05, 2005
    Co-Authors: Anthony Leroy, Frédéric Robert, Francky Catthoor, Pol Marchal, Adelina Shickova, Diederik Verkest
    Abstract:

    To ensure low power consumption while maintaining flexibility and performance, future Systems-on-Chip (SoC) will combine several types of processor cores and data memory units of widely different sizes. To interconnect the IPs of these heterogeneous platforms, Networks-on-Chip (NoC) have been proposed as an efficient and scalable alternative to shared buses. NoCs can provide throughput and latency guarantees by establishing virtual circuits between source and Destination. State-of-the-art NoCs currently exploit Time-Division Multiplexing (TDM) to share network resources among virtual circuits, but this typically results in high network area and energy overhead with long circuit set-up time.We propose an alternative solution based on Spatial Division Multiplexing (SDM). This paper describes our first design of an SDM-based network, discusses design alternatives for network implementation and shows why SDM should be better adapted to NoCs than TDM for a limited number of circuits.Our case study clearly illustrates the advantages of our technique over TDM in terms of energy consumption, area overhead, and flexibility. SDM thus deserves to be explored in more depth, and in particular in combination with TDM in a hybrid scheme.