The Experts below are selected from a list of 35436 Experts worldwide ranked by ideXlab platform
R.m. Secareanu - One of the best experts on this subject based on the ideXlab platform.
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The impact of device leakage on Digital Circuits
2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), 2002Co-Authors: R.m. Secareanu, P. ManiarAbstract:The impact of device leakage on the operation of conventional static and dynamic Digital Circuits is presented. Particular focus is on signal integrity, performance degradation, and power dissipation. A first order estimation regarding the expected circuit and system performances for a technology from a leakage standpoint can be defined based on the developed results. Developing an early guidance and discrimination methodology for device design is another target. The ultimate limits for device leakage for any trade-offs among the signal integrity, performance degradation, and power dissipation, can be estimated for any given technology.
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A comparative study of the behavior of NMOS and CMOS Digital Circuits under substrate noise
ICECS 2001. 8th IEEE International Conference on Electronics Circuits and Systems (Cat. No.01EX483), 2001Co-Authors: R.m. Secareanu, T.e. Watrobski, C. Morton, W. Staub, T. Tellier, S. Warner, S. Seabridge, C. Burke, E.g. FriedmanAbstract:A comparative study of the behavior of NMOS and CMOS Digital Circuits in terms of the ability to tolerate substrate noise is presented. Theoretical and simulation results are confirmed by experimental data gathered from the analysis of NMOS and CMOS test chips. It is shown that while the noise sensitivity of NMOS Digital Circuits is influenced by a variety of factors, the primary phenomenon responsible for the noise integrity of the CMOS Digital Circuits is latch-up.
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Physical design to improve the noise immunity of Digital Circuits in a mixed-signal smart-power system
2000 IEEE International Symposium on Circuits and Systems (ISCAS), 2000Co-Authors: R.m. Secareanu, T.e. Watrobski, C. Morton, W. Staub, S. Warner, S. Seabridge, C. Burke, T. Teilier, E.g. FriendmanAbstract:Theoretical, simulation and experimental analysis and data are presented, discussing physical design techniques which influence the noise behavior of Digital Circuits in a mixed-signal smart-power system. Several physical design strategies are presented to improve the noise immunity of Digital Circuits in smart-power systems.
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The behavior of Digital Circuits under substrate noise in a mixed-signal smart-power environment
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312), 1999Co-Authors: R.m. Secareanu, I.s. Kourtev, J. Becerra, T.e. Watrobski, C. Morton, W. Staub, T. Tellier, E.g. FriedmanAbstract:The behavior of Digital Circuits in a noisy environment in mixed-signal smart-power systems is described in this paper. Several models and mechanisms explaining the process in which substrate noise affects on-chip Digital Circuits as well as the noise immunity behavior of Digital Circuits are presented and discussed. The models and mechanisms are demonstrated by simulations and by extensive test chip-based experimental data.
Mohamed I. Elmasry - One of the best experts on this subject based on the ideXlab platform.
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power dissipation analysis and optimization of deep submicron cmos Digital Circuits
IEEE Journal of Solid-state Circuits, 1996Co-Authors: Richard X. Gu, Mohamed I. ElmasryAbstract:This paper introduces a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS Digital Circuits. The model is based on Berkeley Short-Channel IGFET model and fits HSPICE simulation results well. Static and dynamic power analysis for various threshold voltages is addressed. A design methodology to minimize the power-delay product by selecting the lower and upper bounds of the supply and threshold voltages is presented. The effects of the supply voltage, the threshold voltage, and /spl eta/, which reflects the drain induced barrier lowering, are also addressed.
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Power dissipation analysis and optimization of deep submicron CMOS Digital Circuits
IEEE Journal of Solid-State Circuits, 1996Co-Authors: Richard X. Gu, Mohamed I. ElmasryAbstract:This paper introduces a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS Digital Circuits. The model is based on Berkeley Short-Channel IGFET model and fits HSPICE simulation results well. Static and dynamic power analysis for various threshold voltages is addressed. A design methodology to minimize the power-delay product by selecting the lower and upper bounds of the supply and threshold voltages is presented. The effects of the supply voltage, the threshold voltage, and η, which reflects the drain induced barrier lowering, are also addressed
E.g. Friendman - One of the best experts on this subject based on the ideXlab platform.
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Physical design to improve the noise immunity of Digital Circuits in a mixed-signal smart-power system
2000 IEEE International Symposium on Circuits and Systems (ISCAS), 2000Co-Authors: R.m. Secareanu, T.e. Watrobski, C. Morton, W. Staub, S. Warner, S. Seabridge, C. Burke, T. Teilier, E.g. FriendmanAbstract:Theoretical, simulation and experimental analysis and data are presented, discussing physical design techniques which influence the noise behavior of Digital Circuits in a mixed-signal smart-power system. Several physical design strategies are presented to improve the noise immunity of Digital Circuits in smart-power systems.
W. Staub - One of the best experts on this subject based on the ideXlab platform.
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A comparative study of the behavior of NMOS and CMOS Digital Circuits under substrate noise
ICECS 2001. 8th IEEE International Conference on Electronics Circuits and Systems (Cat. No.01EX483), 2001Co-Authors: R.m. Secareanu, T.e. Watrobski, C. Morton, W. Staub, T. Tellier, S. Warner, S. Seabridge, C. Burke, E.g. FriedmanAbstract:A comparative study of the behavior of NMOS and CMOS Digital Circuits in terms of the ability to tolerate substrate noise is presented. Theoretical and simulation results are confirmed by experimental data gathered from the analysis of NMOS and CMOS test chips. It is shown that while the noise sensitivity of NMOS Digital Circuits is influenced by a variety of factors, the primary phenomenon responsible for the noise integrity of the CMOS Digital Circuits is latch-up.
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Physical design to improve the noise immunity of Digital Circuits in a mixed-signal smart-power system
2000 IEEE International Symposium on Circuits and Systems (ISCAS), 2000Co-Authors: R.m. Secareanu, T.e. Watrobski, C. Morton, W. Staub, S. Warner, S. Seabridge, C. Burke, T. Teilier, E.g. FriendmanAbstract:Theoretical, simulation and experimental analysis and data are presented, discussing physical design techniques which influence the noise behavior of Digital Circuits in a mixed-signal smart-power system. Several physical design strategies are presented to improve the noise immunity of Digital Circuits in smart-power systems.
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The behavior of Digital Circuits under substrate noise in a mixed-signal smart-power environment
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312), 1999Co-Authors: R.m. Secareanu, I.s. Kourtev, J. Becerra, T.e. Watrobski, C. Morton, W. Staub, T. Tellier, E.g. FriedmanAbstract:The behavior of Digital Circuits in a noisy environment in mixed-signal smart-power systems is described in this paper. Several models and mechanisms explaining the process in which substrate noise affects on-chip Digital Circuits as well as the noise immunity behavior of Digital Circuits are presented and discussed. The models and mechanisms are demonstrated by simulations and by extensive test chip-based experimental data.
T.e. Watrobski - One of the best experts on this subject based on the ideXlab platform.
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A comparative study of the behavior of NMOS and CMOS Digital Circuits under substrate noise
ICECS 2001. 8th IEEE International Conference on Electronics Circuits and Systems (Cat. No.01EX483), 2001Co-Authors: R.m. Secareanu, T.e. Watrobski, C. Morton, W. Staub, T. Tellier, S. Warner, S. Seabridge, C. Burke, E.g. FriedmanAbstract:A comparative study of the behavior of NMOS and CMOS Digital Circuits in terms of the ability to tolerate substrate noise is presented. Theoretical and simulation results are confirmed by experimental data gathered from the analysis of NMOS and CMOS test chips. It is shown that while the noise sensitivity of NMOS Digital Circuits is influenced by a variety of factors, the primary phenomenon responsible for the noise integrity of the CMOS Digital Circuits is latch-up.
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Physical design to improve the noise immunity of Digital Circuits in a mixed-signal smart-power system
2000 IEEE International Symposium on Circuits and Systems (ISCAS), 2000Co-Authors: R.m. Secareanu, T.e. Watrobski, C. Morton, W. Staub, S. Warner, S. Seabridge, C. Burke, T. Teilier, E.g. FriendmanAbstract:Theoretical, simulation and experimental analysis and data are presented, discussing physical design techniques which influence the noise behavior of Digital Circuits in a mixed-signal smart-power system. Several physical design strategies are presented to improve the noise immunity of Digital Circuits in smart-power systems.
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The behavior of Digital Circuits under substrate noise in a mixed-signal smart-power environment
11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312), 1999Co-Authors: R.m. Secareanu, I.s. Kourtev, J. Becerra, T.e. Watrobski, C. Morton, W. Staub, T. Tellier, E.g. FriedmanAbstract:The behavior of Digital Circuits in a noisy environment in mixed-signal smart-power systems is described in this paper. Several models and mechanisms explaining the process in which substrate noise affects on-chip Digital Circuits as well as the noise immunity behavior of Digital Circuits are presented and discussed. The models and mechanisms are demonstrated by simulations and by extensive test chip-based experimental data.
