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Bahram Jalali - One of the best experts on this subject based on the ideXlab platform.

  • Digital broadband linearization technique and its application to photonic time stretch analog to Digital Converter
    Optics Letters, 2011
    Co-Authors: Ali Fard, Shalabh Gupta, Bahram Jalali
    Abstract:

    Suppression of distortion induced by nonlinearity in a dynamical system (such as an analog optical link) is very challenging, particularly for a wide-bandwidth signal. Conventional compensation techniques are computationally intensive, significantly limiting their realization in real-time applications. Here, we propose and demonstrate an efficient Digital postprocessing technique to suppress distortions added to a wideband signal by a nonlinear system with memory effect. Experimentally, Digital broadband linearization of the photonic time-stretch analog-to-Digital Converter (TSADC) is demonstrated. In case of TSADC, a dynamic range improvement of >15 dB compared to conventional memory-less correction method is achieved.

  • time warp correction and calibration in photonic time stretch analog to Digital Converter
    Optics Letters, 2008
    Co-Authors: Shalabh Gupta, Bahram Jalali
    Abstract:

    We show how time warps caused by nonuniform wavelength-to-time mapping in the photonic time-stretch analog-to-Digital Converter (ADC) can be Digitally measured and removed. This is combined with Digital correction of wavelength-dependent Mach-Zehnder modulator (MZM) bias offset to attain a 10 GHz bandwidth digitizer with >7 effective bits of resolution and 52 dB spur-free dynamic range. To the best of our knowledge, this is the highest resolution ADC in 10 GHz bandwidth range, with at least 1 order of magnitude higher signal-to-noise ratio than ever achieved. We also demonstrate concatenation of 30 wavelength interleaved time segments with high fidelity on the path to achieving continuous time operation.

  • 130 gsa s photonic analog to Digital Converter with time stretch preprocessor
    IEEE Photonics Technology Letters, 2002
    Co-Authors: A S Bhushan, Bahram Jalali, P V Kelkar, Ozdal Boyraz, M N Islam
    Abstract:

    In this letter, we demonstrate a photonic analog-to-Digital Converter with time stretch (TS) preprocessor that has a sampling rate of 130 GSa/s. The system has a signal-to-noise ratio (SNR) exceeding seven effective number of bits over a 1-GHz bandwidth at 18 GHz. We present an analytical model of the SNR in the TS preprocessor which shows that over the specified bandwidth, the SNR is limited by the amplified spontaneous emission beat noise.

  • Optical folding-flash analog-to-Digital Converter with analog encoding.
    Optics Letters, 1995
    Co-Authors: Bahram Jalali, Y. M. Xie
    Abstract:

    We describe an optically assisted folding-flash analog-to-Digital Converter. The periodic transfer function of the Mach–Zehnder interferometer is used to perform analog folding on the electronic signal to be quantized. A novel analog encoding scheme for efficient generation of gray code Digital data is proposed. The new encoding scheme eliminates the requirement for interferometers with ultralow Vπ, which, so far, has hindered the development of such systems. The encoding concept is experimentally demonstrated through the use of LiNbO3 modulators.

S H Lewis - One of the best experts on this subject based on the ideXlab platform.

  • a level crossing analog to Digital Converter with triangular dither
    IEEE Transactions on Circuits and Systems, 2009
    Co-Authors: Tunde Wang, Dong Wang, P J Hurst, Bernard C Levy, S H Lewis
    Abstract:

    In this paper, a level-crossing analog-to-Digital Converter is described. It can convert audio bandwidth signals with high resolution using few threshold levels and Digital interpolation. Samples are generated at nonuniform time intervals and then interpolated to produce uniformly spaced output samples. A periodic triangular dither signal added to the input ensures that low-amplitude or slowly varying signals are sampled and converted accurately. The dither is estimated and removed Digitally before interpolation. Simulations show that greater than 10-bit resolution can be achieved with only seven comparators when using a sixth-order polynomial interpolator.

  • an 8 bit 80 msample s pipelined analog to Digital Converter with background calibration
    IEEE Journal of Solid-state Circuits, 2001
    Co-Authors: Jun Ming, S H Lewis
    Abstract:

    An 8-bit 80-Msample/s pipelined analog-to-Digital Converter (ADC) uses monolithic background calibration to reduce the nonlinearity caused by interstage gain errors. Test results show that the ADC achieves a peak signal-to-noise-and-distortion ratio of 43.8 dB, a peak integral nonlinearity of 0.51 least significant bit (LSB), and a peak differential nonlinearity of 0.32 LSB with active background calibration. It dissipates 268 mW from a 3 V supply and occupies 10.3 mm/sup 2/ in a single-poly 0.5 /spl mu/m CMOS technology.

  • a 10 b 20 msample s analog to Digital Converter
    IEEE Journal of Solid-state Circuits, 1992
    Co-Authors: S H Lewis, H S Fetterma, G Gross, R Ramachandra, T R Viswanatha
    Abstract:

    A 10-b 20-Msample/s analog-to-Digital Converter fabricated in a 0.9- mu m CMOS technology is described. The Converter uses a pipelined nine-stage architecture with fully differential analog circuits and achieves a signal-to-noise-and-distortion ratio (SNDR) of 60 dB with a full-scale sinusoidal input at 5 MHz. It occupies a 8.7 mm/sup 2/ and dissipates 240 mW. >

Huaijin Chen - One of the best experts on this subject based on the ideXlab platform.

  • a 106 db snr hybrid oversampling analog to Digital Converter for Digital audio
    IEEE Journal of Solid-state Circuits, 2005
    Co-Authors: Khiem Quang Nguyen, R Adams, Karl Sweetland, Huaijin Chen
    Abstract:

    An audio /spl Sigma//spl Delta/ analog-to-Digital Converter (ADC) with the loop filter implemented by continuous-time (CT) and discrete-time (DT) circuits is presented. A tuning circuit is used to compensate for changes in the RC product due to process skew, power supply, temperature and sampling rate variation. To eliminate errors caused by inter-symbol interference (ISI) in the CT feedback DAC, a return-to-zero (RTZ) switching scheme is applied on the error current of the CT integrator. The Converter is fabricated in a 0.35-/spl mu/m CMOS process, and achieves 106-dB dynamic range, -99-dB THD+N.

  • a 106 db snr hybrid oversampling analog to Digital Converter for Digital audio
    International Solid-State Circuits Conference, 2005
    Co-Authors: Khiem Quang Nguyen, R Adams, Karl Sweetland, Huaijin Chen
    Abstract:

    An audio ΣΔ analog-to-Digital Converter (ADC) with the loop filter implemented by continuous-time (CT) and discrete-time (DT) circuits is presented. A tuning circuit is used to compensate for changes in the RC product due to process skew, power supply, temperature and sampling rate variation. To eliminate errors caused by inter-symbol interference (ISI) in the CT feedback DAC, a return-to-zero (RTZ) switching scheme is applied on the error current of the CT integrator. The Converter is fabricated in a 0.35-μm CMOS process, and achieves 106-dB dynamic range, -99-dB THD + N.

Jagadeesh V Kumar - One of the best experts on this subject based on the ideXlab platform.

  • Successive approximation type Digital Converter for floating-wiper inductive displacement sensor
    2017 Eleventh International Conference on Sensing Technology (ICST), 2017
    Co-Authors: Aparna Mohan, S Mohanasankar, Jagadeesh V Kumar
    Abstract:

    A successive approximation type direct displacement to Digital Converter suitable for a floating-wiper inductive displacement sensor is proposed here. The topology of a successive approximation type Digital Converter (SADC) is suitably altered so that a floating-wiper inductive displacement sensor becomes an integral part of the SADC. The successive approximation logic results in the final Digital output directly proportional to the displacement of the floating wiper. The hardware and logic are so designed that the final Digital output is independent of the interfering inputs. The results obtained from simulation studies establish the efficacy of the proposed technique.

  • Linearizing Dual-Slope Digital Converter Suitable for a Thermistor
    IEEE Transactions on Instrumentation and Measurement, 2011
    Co-Authors: Madhu N. Mohan, Jagadeesh V Kumar, P Sankaran
    Abstract:

    To measure temperature using a thermistor as the sensing element, linearization to compensate for the inverse exponential nature of the resistance-temperature characteristic of the thermistor is required. A linearizing dual-slope Digital Converter (LDSDC) that accepts a thermistor sensor as input and provides a Digital output that is directly proportional to the temperature being sensed is presented here. A logarithmic amplifier at the input of the LDSDC compensates for the exponential characteristics. The conversion logic of the underlying dual-slope Converter is suitably modified to implement the required inversion and offset correction and thus obtain linearization over a wide range of input temperature. The efficacy of the proposed LDSDC is established through simulation studies and its practicality demonstrated with experimental results obtained on a prototype unit built and tested. Analysis of the proffered method to identify possible sources of errors is also presented.

  • Direct Digital Converter for a single active element resistive sensor
    2009 IEEE Instrumentation and Measurement Technology Conference, 2009
    Co-Authors: Madhu N. Mohan, Jagadeesh V Kumar
    Abstract:

    A direct Digital Converter that provides a Digital output, proportional to the measurand being sensed by a single active element resistive sensor is presented in this paper. To accomplish this task, the structure and the switching sequence of a conventional dual slope, analog to Digital Converter (DSADC) is appropriately altered so that the altered DSADC accepts the resistance of the sensor as an integral part and provides a Digital output that is linearly proportional to the physical quantity being sensed by the resistive sensor. Since the output of the dual slope resistance to Digital Converter (DSRDC) is dictated only by the magnitudes of a pair of DC reference voltages, a fixed value resistor and the transformation constant of the sensor, the error in the output is minimal. Hence, a high level of linearity and accuracy is achieved. Simulation studies establish the efficacy of the proposed scheme.

  • Dual Slope Resistance to Digital Converter
    2007 IEEE Instrumentation & Measurement Technology Conference IMTC 2007, 2007
    Co-Authors: Madhu N. Mohan, Boby George, Jagadeesh V Kumar
    Abstract:

    A dual slope resistance to Digital Converter applicable to differential resistive sensors is presented. A dual slope Digital Converter is appropriately modified so that it accepts directly the resistive elements of a differential resistive sensor and provide a Digital output that is linearly proportional to the physical quantity being sensed by the sensor. High accuracy is easily obtained since the output is decided only by a pair of dc reference voltages and the transformation constant of the sensor. Sensitivity analysis shows that the effect of circuit parameter variations on the output is minimal. The efficacy of the proposed scheme is clearly demonstrated by the test results obtained on a prototype.

P R Gray - One of the best experts on this subject based on the ideXlab platform.

  • a 1 5 v 10 bit 14 3 ms s cmos pipeline analog to Digital Converter
    IEEE Journal of Solid-state Circuits, 1999
    Co-Authors: A M Abo, P R Gray
    Abstract:

    A 1.5-V, 10-bit, 14.3-MS/s pipeline analog-to-Digital Converter was implemented in a 0.6 /spl mu/m CMOS technology. Emphasis was placed on observing device reliability constraints at low voltage. MOS switches were implemented without low-threshold devices by using a bootstrapping technique that does not subject the devices to large terminal voltages. The Converter achieved a peak signal-to-noise-and-distortion ratio of 58.5 dB, maximum differential nonlinearity of 11.5 least significant bit (LSB), maximum integral nonlinearity of 0.7 LSB, and a power consumption of 36 mW.