The Experts below are selected from a list of 945 Experts worldwide ranked by ideXlab platform

Kenichi Yoshida - One of the best experts on this subject based on the ideXlab platform.

  • Industry Industry/Government Track Paper Track Paper Density-Based Spam Detector
    2013
    Co-Authors: Kenichi Yoshida, Fuminori Adachi, Takashi Washio, Teruaki Homma, Hiromitsu Fujikawa, Katsuyuki Yamazaki
    Abstract:

    The volume of mass unsolicited electronic mail, often known as spam, has recently increased enormously and has become a serious threat to not only the Internet but also to society. This paper proposes a new spam detection method which uses document space density information. Although it requires extensive e-mail traffic to acquire the necessary information, an unsupervised learning engine with a short white list can achieve a 98 % recall rate and 100 % precision. A Direct-Mapped Cache method contributes handling of over 13,000 e-mails per second. Experimental results, which were conducted using over 50 million actual e-mails of traffic, are also reported in this paper

  • Similar video detection using multiple Direct-Mapped Cache
    International Journal of Intelligent Systems Technologies and Applications, 2013
    Co-Authors: Noboru Murabayashi, Kenichi Yoshida
    Abstract:

    Recently, the importance of video detection technology has increased. In our earlier studies, we had proposed the single Direct-Mapped Cache method based on the RGB colour space feature to handle the processing of a large amount of videos on the internet. Although our method achieved a high processing speed, the detection accuracy had room for improvement. In this paper, we propose a new method to improve the accuracy. For this purpose, the combination of MPEG-7 video signature and the multiple Direct-Mapped Cache method is used. The experimental results show that the average detection accuracy is 95% and the processing time is 0.2 seconds for each video. These results indicate a 29% improvement in accuracy over the previous method. The possibility of handling 136 years worth of video data while keeping the same accuracy and processing speed is also one of the unique features of the proposed method.

  • copied video detection with mpeg 7 video signature and multiple Direct Mapped Cache
    International Conference Hybrid Intelligent Systems, 2011
    Co-Authors: Noboru Murabayashi, Kenichi Yoshida
    Abstract:

    According to the increasing popularity of video-sharing websites, copyright infringed videos have become a critical issue. These videos are not only original ones, but also copied ones. Under these circumstances, the importance of video detection technology has increased. In our earlier studies, we had proposed the (single) Direct-Mapped Cache method based on the RGB color space feature to handle the processing of a large amount of videos on the Internet. Although our method achieved a high processing speed, the detection accuracy had room for improvement. In this paper, we proposed a new method to improve the accuracy. For this purpose, the combination of MPEG-7 video signature and the multiple Direct-Mapped Cache method is used. The experimental results show that the average detection accuracy is 95%, and the processing time is 0.2 seconds for each video. These results indicate a 29% improvement in accuracy over the previous method. The possibility of handling 136 years worth of video data while keeping the same accuracy and processing speed is also one of the unique features of the proposed method.

  • HIS - Copied video detection with MPEG-7 video signature and multiple Direct-Mapped Cache
    2011 11th International Conference on Hybrid Intelligent Systems (HIS), 2011
    Co-Authors: Noboru Murabayashi, Kenichi Yoshida
    Abstract:

    According to the increasing popularity of video-sharing websites, copyright infringed videos have become a critical issue. These videos are not only original ones, but also copied ones. Under these circumstances, the importance of video detection technology has increased. In our earlier studies, we had proposed the (single) Direct-Mapped Cache method based on the RGB color space feature to handle the processing of a large amount of videos on the Internet. Although our method achieved a high processing speed, the detection accuracy had room for improvement. In this paper, we proposed a new method to improve the accuracy. For this purpose, the combination of MPEG-7 video signature and the multiple Direct-Mapped Cache method is used. The experimental results show that the average detection accuracy is 95%, and the processing time is 0.2 seconds for each video. These results indicate a 29% improvement in accuracy over the previous method. The possibility of handling 136 years worth of video data while keeping the same accuracy and processing speed is also one of the unique features of the proposed method.

  • KDD - Density-based spam detector
    Proceedings of the 2004 ACM SIGKDD international conference on Knowledge discovery and data mining - KDD '04, 2004
    Co-Authors: Kenichi Yoshida, Fuminori Adachi, Takashi Washio, Hiroshi Motoda, Teruaki Homma, Akihiro Nakashima, Hiromitsu Fujikawa, Katsuyuki Yamazaki
    Abstract:

    The volume of mass unsolicited electronic mail, often known as spam, has recently increased enormously and has become a serious threat to not only the Internet but also to society. This paper proposes a new spam detection method which uses document space density information. Although it requires extensive e-mail traffic to acquire the necessary information, an unsupervised learning engine with a short white list can achieve a 98% recall rate and 100% precision. A Direct-Mapped Cache method contributes handling of over 13,000 e-mails per second. Experimental results, which were conducted using over 50 million actual e-mails of traffic, are also reported in this paper.

Shindug Kim - One of the best experts on this subject based on the ideXlab platform.

  • A small data Cache for multimedia-oriented embedded systems
    Journal of Systems Architecture, 2007
    Co-Authors: Cheong-ghil Kim, Junghoon Lee, Jung-wook Park, Shindug Kim
    Abstract:

    This paper proposes a data Cache with small space for low power, but high performance on multimedia applications. The basic architecture is a split-Cache consisting of a Direct-Mapped Cache with small block size (DMC) and a fully-associative buffer with large block size (FAB). To overcome the disadvantage caused by small Cache areas, two hardware mechanisms are enhanced considering the operational behaviors of multimedia applications: an adaptive multi-block prefetching to initiate various fetch sizes for FAB and an efficient block filtering to remove the data likely to be rarely reused for DMC. The simulations on MediaBench show that the proposed 5kB Cache can achieve up to 57% and 50% of power saving while providing almost equal and better performance compared with the 16kB 4-way set associative Cache and 17kB stream Caches, respectively.

  • A deterministic way-prediction scheme using power-aware replacement policy
    Microprocessors and Microsystems, 2006
    Co-Authors: Jung-wook Park, Gi-ho Park, Sung-bae Park, Shindug Kim
    Abstract:

    Abstract This research is to design a low power set-associative Cache for embedded processors without additional delay or performance degradation. For this goal, deterministic way selection logic with power-aware replacement policy is designed to enable only one way of set-associative Cache as in the Direct-Mapped Cache. Delay analysis shows that the Cache access time is almost the same as that of conventional set associative Cache with additional way selection logic. Proposed architecture exploits the trade-offs between power and performance to achieve power reduction with the least performance loss. As the result of those approaches, simulation shows that the proposed architecture can reduce unit accessing power consumption by 59% over conventional set-associative Caches with average 0.06% of negligible performance loss.

  • An intelligent Cache system with hardware prefetching for high performance
    IEEE Transactions on Computers, 2003
    Co-Authors: Junghoon Lee, Shindug Kim, Seh-woong Jeong, Charles C. Weems
    Abstract:

    We present a high performance Cache structure with a hardware prefetching mechanism that enhances exploitation of spatial and temporal locality. The proposed Cache, which we call a selective-mode intelligent (SMI) Cache, consists of three parts: a Direct-Mapped Cache with a small block size, a fully associative spatial buffer with a large block size, and a hardware prefetching unit. Temporal locality is exploited by selectively moving small blocks into the Direct-Mapped Cache after monitoring their activity in the spatial buffer for a time period. Spatial locality is enhanced by intelligently prefetching a neighboring block when a spatial buffer hit occurs. The overhead of this prefetching operation is shown to be negligible. We also show that the prefetch operation is highly accurate: Over 90 percent of all prefetches generated are for blocks that are subsequently accessed. Our results show that the system enables the Cache size to be reduced by a factor of four to eight relative to a conventional Direct-Mapped Cache while maintaining similar performance. Also, the SMI Cache can reduce the miss ratio by around 20 percent and the average memory access time by 10 percent, compared with a victim-buffer Cache configuration.

  • a new Cache architecture based on temporal and spatial locality
    Journal of Systems Architecture, 2000
    Co-Authors: Junghoon Lee, Jangsoo Lee, Shindug Kim
    Abstract:

    Abstract A data Cache system is designed as low power/high performance Cache structure for embedded processors. Direct-Mapped Cache is a favorite choice for short cycle time, but suffers from high miss rate. Hence the proposed dual data Cache is an approach to improve the miss ratio of Direct-Mapped Cache without affecting this access time. The proposed Cache system can exploit temporal and spatial locality effectively by maximizing the effective Cache memory space for any given Cache size. The proposed Cache system consists of two Caches, i.e., a Direct-Mapped Cache with small block size and a fully associative spatial buffer with large block size. Temporal locality is utilized by caching candidate small blocks selectively into the Direct-Mapped Cache. Also spatial locality can be utilized aggressively by fetching multiple neighboring small blocks whenever a Cache miss occurs. According to the results of comparison and analysis, similar performance can be achieved by using four times smaller Cache size comparing with the conventional Direct-Mapped Cache.And it is shown that power consumption of the proposed Cache can be reduced by around 4% comparing with the victim Cache configuration.

  • ICCD - A selective temporal and aggressive spatial Cache system based on time interval
    Proceedings 2000 International Conference on Computer Design, 1
    Co-Authors: Junghoon Lee, Jangsoo Lee, Shindug Kim
    Abstract:

    This paper proposes a new Cache system that can increase the effect by temporal and spatial locality by using only simple hardware control without any locality detection hardware or compiler aid. The proposed Cache system consists of two Caches with different associativities and different block sizes, i.e., a Direct-Mapped Cache with small block size and a fully associative spatial buffer with large block size as a multiple of small blocks. Therefore, the spatial locality can be exploited by aggressively fetching large blocks including any missed small block into the buffer, and the temporal locality can also be exploited by selectively storing small blocks that were referenced at the spatial buffer in the past. To determine the blocks to be stored at the Direct-Mapped Cache, the proposed Cache system uses a time interval-based selection mechanism. According to the simulation results, similar performance can be achieved by using four times smaller Cache size compared with the conventional Direct-Mapped Cache.

E.l. Zapata - One of the best experts on this subject based on the ideXlab platform.

  • PDP - Direct Mapped Cache performance modeling for sparse matrix operations
    Proceedings of the Seventh Euromicro Workshop on Parallel and Distributed Processing. PDP'99, 1999
    Co-Authors: Rama Doallo, B.b. Fraguela, E.l. Zapata
    Abstract:

    Sparse matrices are in the kernel of numerical applications. Their compressed storage, which permits both operations and memory savings, generates irregular access patterns, reducing the performance of the memory hierarchy In this work we present a probabilistic model for the prediction of the number of misses of a Direct Mapped Cache memory, considering sparse matrices with a uniform entries distribution. The number of misses is Directly related to the program execution time and the memory hierarchy performance. The model considers the three types of standard interferences: intrinsic, self-cross interferences. We explain in detail the modeling of a representative matrix operation such as the sparse matrix-dense matrix product, considering several loop orderings, and include validation results that show the model accuracy.

  • Direct Mapped Cache performance modeling for sparse matrix operations
    Proceedings of the Seventh Euromicro Workshop on Parallel and Distributed Processing. PDP'99, 1999
    Co-Authors: Rama Doallo, B.b. Fraguela, E.l. Zapata
    Abstract:

    Sparse matrices are in the kernel of numerical applications. Their compressed storage, which permits both operations and memory savings, generates irregular access patterns, reducing the performance of the memory hierarchy In this work we present a probabilistic model for the prediction of the number of misses of a Direct Mapped Cache memory, considering sparse matrices with a uniform entries distribution. The number of misses is Directly related to the program execution time and the memory hierarchy performance. The model considers the three types of standard interferences: intrinsic, self-cross interferences. We explain in detail the modeling of a representative matrix operation such as the sparse matrix-dense matrix product, considering several loop orderings, and include validation results that show the model accuracy.

  • Euro-Par - Cache Misses Prediction for High Performance Sparse Algorithms
    Euro-Par’98 Parallel Processing, 1998
    Co-Authors: B.b. Fraguela, Rama Doallo, E.l. Zapata
    Abstract:

    Many scientific applications handle compressed sparse matrices. Cache behavior during the execution of codes with irregular access patterns, such as those generated by this type of matrices, has not been widely studied. In this work a probabilistic model for the prediction of the number of misses on a Direct Mapped Cache memory considering sparse matrices with an uniform distribution is presented. As an example of the potential usability of such types of models, and taking into account the state of the art with respect to high performance superscalar and/or superpipelined CPUs with a multilevel memory hierarchy, we have modeled the Cache behavior of an optimized sparse matrix-dense matrix product algorithm including blocking at the memory and register levels.

Alexandru Nicolau - One of the best experts on this subject based on the ideXlab platform.

  • line size adaptivity analysis of parameterized loop nests for Direct Mapped data Cache
    IEEE Transactions on Computers, 2005
    Co-Authors: Paolo Dalberto, Alexandru Nicolau, Alexander V Veidenbaum, Rajesh Gupta
    Abstract:

    Caches are crucial components of modern processors; they allow high-performance processors to access data fast and, due to their small sizes, they enable low-power processors to save energy - by circumventing memory accesses. We examine efficient utilization of data Caches in an adaptive memory hierarchy. We exploit data reuse through the static analysis of Cache-line size adaptivity. We present an approach that enables the quantification of data misses with respect to Cache-line size at compile-time using (parametric) equations, which model interference. Our approach aims at the analysis of perfect loop nests in scientific applications; it is applied to Direct Mapped Cache and it is an extension and generalization of the Cache miss equation (CME) proposed by Ghosh et al. (1999). Part of this analysis is implemented in a software package, STAMINA. We present analytical results in comparison with simulation-based methods and we show evidence of both the expressiveness and the practicability of the analysis.

  • ICCAD - MIST: an algorithm for memory miss traffic management
    IEEE ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE ACM Digest of Technical Papers (Cat. No.00CH37140), 1
    Co-Authors: Peter Grun, Nikil Dutt, Alexandru Nicolau
    Abstract:

    Cache misses represent a major bottleneck in embedded systems performance. Traditionally, compilers optimistically treated all memory accesses as Cache hits, relying on the memory controller to account for longer miss delays. However, the memory controller has only a local view of the program, and is not able to efficiently hide the latency of these memory operations. Our compiler technique actively manages Cache misses, and performs global miss traffic optimizations, to better hide the latency of the memory operations. Our memory-aware compiler scheduled several benchmarks on the TIC6211 processor architecture with a Direct Mapped Cache, and generated an average of 61.6% improvement over the best schedule of the traditional (memory-transparent) optimizing compiler, demonstrating the utility of our miss traffic optimization approach.

André Seznec - One of the best experts on this subject based on the ideXlab platform.

  • Accurate Data Distribution into Blocks may Boost Cache Performance
    1997
    Co-Authors: Dan Truong, François Bodin, André Seznec
    Abstract:

    Applications often under-utilize Cache space and there are no software locality optimization techniques available for non-scientific applications. We propose that data redistribution in memory be used to modify reference patterns to improve locality of references. To understand the potential of such an approach and to explain where gains come from, we introduce distribution misses, and define a correlation metric to evaluate spatial locality. Data distribution can help reduce capacity and conflict misses in regular Caches, as our experimental results to show. We use as example a profile-based scalar data layout heuristic, which was able to remove up to 76% of the Direct-Mapped Cache miss ratio on some benchmark traces.

  • ICPP (1) - Semi-unified Caches
    1993 International Conference on Parallel Processing - ICPP'93 Vol1, 1993
    Co-Authors: Nathalie Drach, André Seznec
    Abstract:

    The purpose of the semi-unified on-chip Cache organization, is to use the data Cache (resp. ins truction Cache) as an on-chip second-level Cache for instructions (resp. data). Thus the associativity de gree of both on-chip Caches is artificially increased, and the Cache spaces respectively devoted to instruc tions and data are dynamically adjusted. The off-chip miss ratio of a semi-unified Cache built with two DirectMapped Caches of size S is equal to the miss ratio of a unified two-way set associative Cache of size 2S; yet, the hit time of this semi-unified Cache is equal to the hit time of a Direct-Mapped Cache. Trace driven simu lations show that using a Direct-Mapped semi-unified Cache organization leads to higher overall system per formance than using usual split instruction/data Cache organization.

  • Semi-inified Caches
    1993
    Co-Authors: Nathalie Drach, André Seznec
    Abstract:

    Since the gap between main memory access time and processor cycle time is continuously increasing, processor performance dramatically depends on the behavior of Caches and particularly on the behavior of small on-chip Caches. In this paper, we present a new organisation for on-chip Caches : the semi-unified Cache organization. In most microprocessors, two physically split Caches are used for respectively storing data and instructions. The purpose of the semi-unified Cache organization is to use the data Cache (resp. instruction Cache) as an on-chip second-level Cache for instructions (resp. data). Thus the associativity degree of both on-chip Caches is artificially increased and the Cache spaces respectively devoted to instructions and data are dynamically adjusted. The off-chip miss ratio of a semi-unified Cache built with two Direct-Mapped Caches of size S is equal to the miss ratio of a unified two-way set associative Cache of size 2S ; yet, the hit time of this semi-unified Cache is equal to the hit time of a Direct-Mapped Cache ; moreover both instructions and data may be accessed in parallel as for the split data/instruction Cache organization. Since on-chip miss penalty is lower than off-chip miss penalty, trace driven simulations show that using a Direct-Mapped semi-unified Cache organization leads to higher overall system performance than using usual split instruction/data Cache organization.