The Experts below are selected from a list of 318 Experts worldwide ranked by ideXlab platform

Doru Florin Chiper - One of the best experts on this subject based on the ideXlab platform.

  • a new systolic array algorithm and architecture for the vlsi implementation of idst based on a pseudo band correlation structure
    Advances in Electrical and Computer Engineering, 2017
    Co-Authors: Doru Florin Chiper, Arcadie Cracan, D Burdia
    Abstract:

    In this paper a new linear VLSI array architecture for the VLSI implementation of a prime-length 1-D Inverse Discrete Sine Transform (IDST) is proposed. This new design approach uses a ...

  • A novel algorithm and architecture for a high-throughput VLSI implementation of DST using short pseudo-cycle convolutions
    2017 International Symposium on Signals Circuits and Systems (ISSCS), 2017
    Co-Authors: Doru Florin Chiper, Arcadie Cracan
    Abstract:

    Using a new input restructuring sequence and an appropriate reordering of the elements involved, a new VLSI algorithm that uses short length pseudo-cycle convolution structures for the VLSI implementation of Discrete Sine Transform is presented. It uses a new parallel decomposition of Discrete Sine Transform (DST) that leads to a high throughput VLSI implementation with a low hardware cost. The proposed algorithm is efficiently mapped onto two linear systolic arrays that have a modular and regular structure with a a low I/O cost and local and regular interconnections. Thus, an efficient VLSI implementation with high performances can be obtained.

  • systolic algorithms and a memory based design approach for a unified architecture for the computation of dct dst idct idst
    IEEE Transactions on Circuits and Systems, 2005
    Co-Authors: Doru Florin Chiper, M N S Swamy, M.o. Ahmad, T Stouraitis
    Abstract:

    In this paper, an efficient design approach for a unified very large-scale integration (VLSI) implementation of the Discrete coSine Transform/Discrete Sine Transform/inverse Discrete coSine Transform/inverse Discrete Sine Transform based on an appropriate formulation of the four Transforms into cyclic convolution structures is presented. This formulation allows an efficient memory-based systolic array implementation of the unified architecture using dual-port ROMs and appropriate hardware sharing methods. The performance of the unified design is compared to that of some of the existing ones. It is found that the proposed design provides a superior performance in terms of the hardware complexity, speed, I/O costs, in addition to such features as regularity, modularity, pipelining capability, and local connectivity, which make the unified structure well suited for VLSI implementation.

  • Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST
    IEEE Transactions on Circuits and Systems I: Regular Papers, 2005
    Co-Authors: Doru Florin Chiper, M N S Swamy, M.o. Ahmad, Thanos Stouraitis
    Abstract:

    In this paper, an efficient design approach for a unified very large-scale integration (VLSI) implementation of the Discrete coSine Transform/Discrete Sine Transform/inverse Discrete coSine Transform/inverse Discrete Sine Transform based on an appropriate formulation of the four Transforms into cyclic convolution structures is presented. This formulation allows an efficient memory-based systolic array implementation of the unified architecture using dual-port ROMs and appropriate hardware sharing methods. The performance of the unified design is compared to that of some of the existing ones. It is found that the proposed design provides a superior performance in terms of the hardware complexity, speed, I/O costs, in addition to such features as regularity, modularity, pipelining capability, and local connectivity, which make the unified structure well suited for VLSI implementation.

  • A systolic array architecture for the Discrete Sine Transform
    IEEE Transactions on Signal Processing, 2002
    Co-Authors: Doru Florin Chiper, M N S Swamy, M.o. Ahmad, Thanos Stouraitis
    Abstract:

    An efficient approach to design very large scale integration (VLSI) architectures and a scheme for the implementation of the Discrete Sine Transform (DST), based on an appropriate decomposition method that uses circular correlations, is presented. The proposed design uses an efficient restructuring of the computation of the DST into two circular correlations, having similar structures and only one half of the length of the original Transform; these can be concurrently computed and mapped onto the same systolic array. Significant improvement in the computational speed can be obtained at a reduced input-output (I/O) cost and low hardware complexity, retaining all the other benefits of the VLSI implementations of the Discrete Transforms, which use circular correlation or cyclic convolution structures. These features are demonstrated by comparing the proposed design with some of the previously reported schemes.

M N S Swamy - One of the best experts on this subject based on the ideXlab platform.

  • New Systolic Algorithm and Array Architecture for Prime-Length Discrete Sine Transform
    IEEE Transactions on Circuits and Systems II: Express Briefs, 2007
    Co-Authors: Pramod Kumar Meher, M N S Swamy
    Abstract:

    Using a simple input-regeneration approach and index-Transformation techniques, a new formulation is presented in this paper for computing an N-point prime-length Discrete Sine Transform (DST) through two pairs of [(N-1)/4]-point cyclic convolutions, where [(N-1)/4] is an odd number. The cyclic convolution-based algorithm is used further to obtain a simple regular and locally connected linear systolic array for concurrent pipelined implementation of the DST. It is shown that the proposed systolic structure involves significantly less area-time complexity compared with that of the existing structures

  • reduced complexity concurrent systolic implementation of the Discrete Sine Transform
    Asia Pacific Conference on Circuits and Systems, 2006
    Co-Authors: Pramod Kumar Meher, A P Vinod, Jagdish C Patra, M N S Swamy
    Abstract:

    In this paper, a reduced complexity algorithm for computation of the Discrete Sine Transform (DST) is presented. The proposed algorithm can be used to compute an N?point DST from two pairs of [(M ? 1)/2]?point identical cyclic convolutions, where M is a prime number and M = N/2. A regular and locally connected linear systolic array architecture is also presented for concurrent pipelined VLSI implementation of all the four cyclic convolutions. The proposed structure is not only simpler, but also involves significantly less area-time complexity compared to that of the existing convolution-based DST structures. Unlike some of the existing structures, it does not need any control tag-bits for implementation of convolution-like operations.

  • APCCAS - Reduced-Complexity Concurrent Systolic Implementation of the Discrete Sine Transform
    APCCAS 2006 - 2006 IEEE Asia Pacific Conference on Circuits and Systems, 2006
    Co-Authors: Pramod Kumar Meher, A P Vinod, Jagdish C Patra, M N S Swamy
    Abstract:

    In this paper, a reduced complexity algorithm for computation of the Discrete Sine Transform (DST) is presented. The proposed algorithm can be used to compute an N?point DST from two pairs of [(M ? 1)/2]?point identical cyclic convolutions, where M is a prime number and M = N/2. A regular and locally connected linear systolic array architecture is also presented for concurrent pipelined VLSI implementation of all the four cyclic convolutions. The proposed structure is not only simpler, but also involves significantly less area-time complexity compared to that of the existing convolution-based DST structures. Unlike some of the existing structures, it does not need any control tag-bits for implementation of convolution-like operations.

  • systolic algorithms and a memory based design approach for a unified architecture for the computation of dct dst idct idst
    IEEE Transactions on Circuits and Systems, 2005
    Co-Authors: Doru Florin Chiper, M N S Swamy, M.o. Ahmad, T Stouraitis
    Abstract:

    In this paper, an efficient design approach for a unified very large-scale integration (VLSI) implementation of the Discrete coSine Transform/Discrete Sine Transform/inverse Discrete coSine Transform/inverse Discrete Sine Transform based on an appropriate formulation of the four Transforms into cyclic convolution structures is presented. This formulation allows an efficient memory-based systolic array implementation of the unified architecture using dual-port ROMs and appropriate hardware sharing methods. The performance of the unified design is compared to that of some of the existing ones. It is found that the proposed design provides a superior performance in terms of the hardware complexity, speed, I/O costs, in addition to such features as regularity, modularity, pipelining capability, and local connectivity, which make the unified structure well suited for VLSI implementation.

  • Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST
    IEEE Transactions on Circuits and Systems I: Regular Papers, 2005
    Co-Authors: Doru Florin Chiper, M N S Swamy, M.o. Ahmad, Thanos Stouraitis
    Abstract:

    In this paper, an efficient design approach for a unified very large-scale integration (VLSI) implementation of the Discrete coSine Transform/Discrete Sine Transform/inverse Discrete coSine Transform/inverse Discrete Sine Transform based on an appropriate formulation of the four Transforms into cyclic convolution structures is presented. This formulation allows an efficient memory-based systolic array implementation of the unified architecture using dual-port ROMs and appropriate hardware sharing methods. The performance of the unified design is compared to that of some of the existing ones. It is found that the proposed design provides a superior performance in terms of the hardware complexity, speed, I/O costs, in addition to such features as regularity, modularity, pipelining capability, and local connectivity, which make the unified structure well suited for VLSI implementation.

Ali Ozen - One of the best experts on this subject based on the ideXlab platform.

  • a novel waveform design based on Discrete Sine Transform for 5g and beyond
    International Conference on Telecommunications, 2018
    Co-Authors: Yasin Kus, Mukremin Kavlak, Ugur Elmagoz, Ali Ozen
    Abstract:

    In this paper, it is proposed a new unique word (UW) OFDM waveform based on zero-tail Discrete Sine Transform spread OFDM (ZT UW DST-S OFDM). The proposed waveform improves the ZT DST-S-OFDM and UW OFDM methods by removing the influence of the data symbols on the tail of the transmitted signal. In this study, the effects of different UW sequences such as Zadoff-Chu, CAZAC, 15 bit PN, 8 bit complementary code keying (CCK), 0-word, 1-word and −1-word on the bit error rate (BER) and channel tracking (Doppler) performance of the proposed ZT UW DST-S OFDM systems are investigated. In order to test the performance of the proposed method, computer simulation studies are performed on time invariant and time variant frequency selective Rayleigh fading channels. The obtained results confirm that the proposed waveform has better BER and channel tracking (Doppler) performance than the conventional OFDM and ZT DFT-S OFDM systems. In particular, it is observed that the ZT UW DST-S OFDM using Zadoff-Chu sequence has the best BER and channel tracking performance.

  • zero tail unique word Discrete Sine Transform spread ofdm
    Signal Processing and Communications Applications Conference, 2018
    Co-Authors: Yasin Kus, Mukremin Kavlak, Ugur Elmagoz, Ali Ozen
    Abstract:

    In this paper, it is proposed a new unique word (UW) OFDM waveform based on zero-tail Discrete Sine Transform spread OFDM (ZT UW DST-S OFDM). The proposed waveform improves the ZT DST-S-OFDM and UW OFDM methods by removing the influence of the data symbols on the tail of the transmitted signal. In order to test the performance of the proposed method, computer simulation studies are performed on frequency selective Rayleigh fading channels. The obtained results confirm that the proposed waveform has better peak to average power ratio (PAPR) and bit error rate (BER) performance than the conventional OFDM, ZT DFT-S OFDM and ZT UW DFT-S OFDM systems.

  • SIU - Zero tail unique word Discrete Sine Transform spread OFDM
    2018 26th Signal Processing and Communications Applications Conference (SIU), 2018
    Co-Authors: Yasin Kus, Mukremin Kavlak, Ugur Elmagoz, Ali Ozen
    Abstract:

    In this paper, it is proposed a new unique word (UW) OFDM waveform based on zero-tail Discrete Sine Transform spread OFDM (ZT UW DST-S OFDM). The proposed waveform improves the ZT DST-S-OFDM and UW OFDM methods by removing the influence of the data symbols on the tail of the transmitted signal. In order to test the performance of the proposed method, computer simulation studies are performed on frequency selective Rayleigh fading channels. The obtained results confirm that the proposed waveform has better peak to average power ratio (PAPR) and bit error rate (BER) performance than the conventional OFDM, ZT DFT-S OFDM and ZT UW DFT-S OFDM systems.

  • TSP - A Novel Waveform Design Based on Discrete Sine Transform for 5G and Beyond
    2018 41st International Conference on Telecommunications and Signal Processing (TSP), 2018
    Co-Authors: Yasin Kus, Mukremin Kavlak, Ugur Elmagoz, Ali Ozen
    Abstract:

    In this paper, it is proposed a new unique word (UW) OFDM waveform based on zero-tail Discrete Sine Transform spread OFDM (ZT UW DST-S OFDM). The proposed waveform improves the ZT DST-S-OFDM and UW OFDM methods by removing the influence of the data symbols on the tail of the transmitted signal. In this study, the effects of different UW sequences such as Zadoff-Chu, CAZAC, 15 bit PN, 8 bit complementary code keying (CCK), 0-word, 1-word and −1-word on the bit error rate (BER) and channel tracking (Doppler) performance of the proposed ZT UW DST-S OFDM systems are investigated. In order to test the performance of the proposed method, computer simulation studies are performed on time invariant and time variant frequency selective Rayleigh fading channels. The obtained results confirm that the proposed waveform has better BER and channel tracking (Doppler) performance than the conventional OFDM and ZT DFT-S OFDM systems. In particular, it is observed that the ZT UW DST-S OFDM using Zadoff-Chu sequence has the best BER and channel tracking performance.

Thanos Stouraitis - One of the best experts on this subject based on the ideXlab platform.

  • Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST
    IEEE Transactions on Circuits and Systems I: Regular Papers, 2005
    Co-Authors: Doru Florin Chiper, M N S Swamy, M.o. Ahmad, Thanos Stouraitis
    Abstract:

    In this paper, an efficient design approach for a unified very large-scale integration (VLSI) implementation of the Discrete coSine Transform/Discrete Sine Transform/inverse Discrete coSine Transform/inverse Discrete Sine Transform based on an appropriate formulation of the four Transforms into cyclic convolution structures is presented. This formulation allows an efficient memory-based systolic array implementation of the unified architecture using dual-port ROMs and appropriate hardware sharing methods. The performance of the unified design is compared to that of some of the existing ones. It is found that the proposed design provides a superior performance in terms of the hardware complexity, speed, I/O costs, in addition to such features as regularity, modularity, pipelining capability, and local connectivity, which make the unified structure well suited for VLSI implementation.

  • A systolic array architecture for the Discrete Sine Transform
    IEEE Transactions on Signal Processing, 2002
    Co-Authors: Doru Florin Chiper, M N S Swamy, M.o. Ahmad, Thanos Stouraitis
    Abstract:

    An efficient approach to design very large scale integration (VLSI) architectures and a scheme for the implementation of the Discrete Sine Transform (DST), based on an appropriate decomposition method that uses circular correlations, is presented. The proposed design uses an efficient restructuring of the computation of the DST into two circular correlations, having similar structures and only one half of the length of the original Transform; these can be concurrently computed and mapped onto the same systolic array. Significant improvement in the computational speed can be obtained at a reduced input-output (I/O) cost and low hardware complexity, retaining all the other benefits of the VLSI implementations of the Discrete Transforms, which use circular correlation or cyclic convolution structures. These features are demonstrated by comparing the proposed design with some of the previously reported schemes.

Muhammad Aprianda Rahmadi - One of the best experts on this subject based on the ideXlab platform.

  • perancangan dan analisis audio watermarking berbasis Discrete Sine Transform dst dengan metode lifting wavelet Transform lwt dan centroid
    eProceedings of Engineering, 2018
    Co-Authors: Muhammad Aprianda Rahmadi, Gelar Budiman, Irma Safitri
    Abstract:

    Penyebaran informasi dan data digital terutama lagu di internet telah berdampak negatif terhadap perlindungan hak cipta dari lagu tersebut. Untuk melindungi hak cipta pada lagu tersebut, maka di perlukan suatu teknik yang tidak hanya handal, namun tahan terhadap berbagai serangan yaitu teknik audio watermarking. Pada paper ini, dilakukan perancangan dan analisis audio watermarking dengan menggabungkan beberapa metode seperti Discrete Sine Transform (DST), Lifting Wavelet Transform (LWT), dan Centroid. Di metode LWT, Host audio akan di segmentasi melalui dua filter yaitu High Pass Filter (HPF) dan Low Pass Filter (LPF). Setelah itu, host akan di osilasi dengan fungsi sinus amplituda dan frekuensi yang berbeda-beda sehingga korelasi unsur-unsur dari sinyal dapat dihilangkan dan diperoleh sinyal dalam domain frekuensi. Metoda Centroid, digunakan untuk mencari nilai amplituda titik pusat dari sinyal, setalah mendapatkan titik pusat dari centroid lalu watermark disisipkan dengan mengubah titik pusat nya menggunakan teknik QIM. Hasil penelitian ini, menunjukkan bahwa sistem audio watermarking yang dirancang memiliki parameter robustness yang baik terhadap serangan LPF, BPF (25-6k), Resampling, TSM, LSC, Kompresi MP3, dan kompresi MP4 dimana BER yang diperoleh <10 %. Memiliki kapasitas watermark yang besar yaitu 689,0625 bps, dan nilai SNR 24 dB.

  • PERANCANGAN DAN ANALISIS AUDIO WATERMARKING BERBASIS Discrete Sine Transform (DST) DENGAN METODE LIFTING WAVELET Transform (LWT) DAN CENTROID
    Universitas Telkom, 2018
    Co-Authors: Muhammad Aprianda Rahmadi
    Abstract:

    Berbagai persoalan yang ada seperti kepemilikan perlu untuk dilindungi hak cipta dan keasliannya. Audio adalah data digital yang rawan untuk di gandakan dan di sebar luaskan, sehingga data tersebut dapat di klaim oleh orang yang tidak bertanggung jawab. Oleh karena itu, diperlukan suatu teknologi yang dapat mengamankan data digital untuk meminimalisir tindak penyebaran data tersebut, agar memberikan rasa aman kepada pemilik dalam melindungi copyright pada karyanya. Audio watermarking dapat menjadi solusi untuk mengatasi permasalahan tersebut. Audio watermarking adalah teknik untuk menyisipkan informasi ke dalam file audio tanpa mengganggu kualitas file asli nya, dan tidak dapat dilepaskan dengan cara yang biasa. Diharapkan dengan adanya teknik ini dapat memberikan perlindungan terhadap karya-karya audio digital. Pada Tugas Akhir ini kami mengusulkan judul “Perancangan dan Analisis Audio Watermarking Berbasis Discrete Sine Transform (DST) dengan Metode Lifting Wavelet Transform (LWT) dan Centroid”. Hasil penelitian ini, menunjukkan bahwa sistem audio watermarking yang dirancang memiliki parameter ketahanan yang baik terhadap serangan LPF (3K,6K,9K), BPF (25-6k), Resampling (22,05k, 11,025k, 16k), TSM (1%, 2%, 4%), LSC (1%, 5%, 10%), Kompresi MP3 (32k, 64k, 128k, 192k), dan kompresi MP4 (32k, 64k, 128k, 192k) dimana BER yang diperoleh