The Experts below are selected from a list of 42549 Experts worldwide ranked by ideXlab platform
H. Klar - One of the best experts on this subject based on the ideXlab platform.
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A CMOS gate Array Architecture for digital signal processing applications
IEEE Journal of Solid-State Circuits, 1996Co-Authors: J.-m. Green, H. KlarAbstract:A new CMOS gate Array Architecture for digital signal processing (DSP) is presented. The basic cell structure takes into account the high degree of regularity of DSP datapaths. Therefore, it supports in particular the implementation of systolic Arrays in connection with a pipelining scheme of one addition per half clock cycle. Together with a new gate Array approach (macrocell design style), macrocells can be implemented efficiently on the new Architecture. All DSP macrocells use dynamic transmission gate latches. Furthermore, the routing is done exclusively by cell abutment which results in short intercell routing. The macrocell design style is compared with the conventional gate Array approach. In the common gate Array approach, conventional gate Array Architectures are used together with conventional design equipment and layout strategies. The comparison shows a reduction in area and power consumption by a factor of 2.5 and 3.7, respectively. The efficiency increases by a factor of at least nine. These results were proved by analog circuit simulations and test chip measurements.
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MOS Gate Array Architecture for igital Signal Processing Applications
1996Co-Authors: J.-m. Green, H. KlarAbstract:Abstr-ut-A new CMOS gate Array Architecture for digital signal processing (DSP) is presented. The basic cell structure takes into account the high degree of regularity of DSP datapaths. Therefore, it supports in particular the implementation of systolic Arrays in connection with a pipelining scheme of one addition per half clock cycle. Together with a new gate Array approach (macrocell design style), macrocells can be implemented efficiently on the new Architecture. All DSP macrocells use dynamic transmission gate latches. Furthermore, the routing is done exclusively by cell abutment which results in short intercell routing. The macrocell design style is compared with the conventional gate Array approach. In the common gate Array approach, conventional gate Array Architectures are used together with conventional design equipment and layout strategies. The comparison shows a reduction in area and power consumption by a factor of 2.5 and 3.7, respectively. The efficiency increases by a factor of at least nine. These results were proved by analog circuit simulations and test chip measurements.
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CMOS gate Array Architecture for digital signal processing applications
Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, 1Co-Authors: J.-m. Green, H. KlarAbstract:A CMOS gate Array Architecture for digital signal processing (DSP) is presented. The new structure takes into account the high degree of regularity of DSP datapaths and particularly supports the implementation of systolic Arrays in connection with a pipelining scheme of one addition per half clock cycle. This reduces both the area and the power consumption by about 21% and 33%, respectively, compared to conventional gate Arrays.
S S Wong - One of the best experts on this subject based on the ideXlab platform.
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compact one transistor n rram Array Architecture for advanced cmos technology
IEEE Journal of Solid-state Circuits, 2015Co-Authors: Chihwei Stanley Yeh, S S WongAbstract:For RRAM to be a cost-competitive candidate for high-density and high-capacity commercial products, some architectural-level challenges must be tackled. In this paper, research results that advance the design of high-density RRAM Arrays are presented. We first focus on the scaling effects of on-chip interconnects on RRAM Array performance. Due to the continuously shrinking process feature size, the voltage drop along the interconnect gradually reduces the voltage available to operate the RRAM device. To more efficiently analyze this effect for an arbitrary Array size, a compact Array model is developed. Simulations using this model determine the maximum achievable Array size for future technology nodes. A compact, one-transistor-N-RRAM (1TNR) Array Architecture, with corresponding read/write and decoding schemes, that achieves high RRAM density is then introduced. A proof-of-concept 1T4R test chip with fully integrated RRAM devices is described. For this test chip, a particular sequence to form the cross-point RRAM Array is presented. Measurement results of successful Array operations demonstrate the feasibility and reliability of the proposed high-density Architecture.
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Array Architecture for a nonvolatile 3 dimensional cross point resistance change memory
IEEE Journal of Solid-state Circuits, 2011Co-Authors: S S WongAbstract:This work explores the design and capabilities of a three-dimensional cross-point Array structure suitable for use with resistance-change non-volatile memory. The resistance-change cell serves as both the access element and the memory element, eliminating the need for individual selection devices. This work presents novel Architecture and circuit techniques that minimize leakage current effects while maintaining a high effective bit density. A test chip fabricated in 0.18 μm CMOS technology verifies the Architecture and circuit functionality. The performance of an 8 Gb memory chip built in 65 nm technology has been simulated. A random access time of 104 ns is achieved with a power dissipation of 61.2 mW. This makes the 3D cross-point memory competitive with NOR flash in terms of read time, and competitive with NAND flash in terms of area efficiency.
D J Richardson - One of the best experts on this subject based on the ideXlab platform.
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highly scalable amplified hybrid tdm dwdm Array Architecture for interferometric fiber optic sensor systems
Journal of Lightwave Technology, 2013Co-Authors: Yi Liao, Ed Austin, Phillip J Nash, Stuart A Kingsley, D J RichardsonAbstract:We present a distributed amplified hybrid dense wavelength division multiplexing (DWDM) and time division multiplexing (TDM) Array Architecture for large scale interferometric fiber-optic sensor Array systems. This Architecture employs a distributed Erbium doped fiber amplifier (EDFA) scheme to decrease the distribution loss among multiplexed wavelengths, and employs TDM at each wavelength to increase the total number of sensors that can be supported. The first experimental demonstration of this system is reported including results which show the potential for multiplexing and interrogating up to 4096 sensors using a single telemetry fiber pair with good system performance. The number of interrogation sensors could be further increased by increasing the number of wavelength channels. These Architectures would be of great importance in the application of systems requiring very large number of sensors with limited telemetry cabling.
Keikichi Tamaru - One of the best experts on this subject based on the ideXlab platform.
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IPPS - A memory efficient Array Architecture for real-time motion estimation
Proceedings 11th International Parallel Processing Symposium, 1Co-Authors: Vasily G. Moshnyaga, Keikichi TamaruAbstract:A new 2-D Array Architecture for real-time video picture motion estimation is presented. Due to incorporated concepts of video memory distribution and sharing, the Architecture ensures feasible solutions for the HDTV picture format with lower memory requirements. It features minimal I/O pin count, 100% processor utilization and is quite suitable for VLSI implementation.
J.-m. Green - One of the best experts on this subject based on the ideXlab platform.
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A CMOS gate Array Architecture for digital signal processing applications
IEEE Journal of Solid-State Circuits, 1996Co-Authors: J.-m. Green, H. KlarAbstract:A new CMOS gate Array Architecture for digital signal processing (DSP) is presented. The basic cell structure takes into account the high degree of regularity of DSP datapaths. Therefore, it supports in particular the implementation of systolic Arrays in connection with a pipelining scheme of one addition per half clock cycle. Together with a new gate Array approach (macrocell design style), macrocells can be implemented efficiently on the new Architecture. All DSP macrocells use dynamic transmission gate latches. Furthermore, the routing is done exclusively by cell abutment which results in short intercell routing. The macrocell design style is compared with the conventional gate Array approach. In the common gate Array approach, conventional gate Array Architectures are used together with conventional design equipment and layout strategies. The comparison shows a reduction in area and power consumption by a factor of 2.5 and 3.7, respectively. The efficiency increases by a factor of at least nine. These results were proved by analog circuit simulations and test chip measurements.
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MOS Gate Array Architecture for igital Signal Processing Applications
1996Co-Authors: J.-m. Green, H. KlarAbstract:Abstr-ut-A new CMOS gate Array Architecture for digital signal processing (DSP) is presented. The basic cell structure takes into account the high degree of regularity of DSP datapaths. Therefore, it supports in particular the implementation of systolic Arrays in connection with a pipelining scheme of one addition per half clock cycle. Together with a new gate Array approach (macrocell design style), macrocells can be implemented efficiently on the new Architecture. All DSP macrocells use dynamic transmission gate latches. Furthermore, the routing is done exclusively by cell abutment which results in short intercell routing. The macrocell design style is compared with the conventional gate Array approach. In the common gate Array approach, conventional gate Array Architectures are used together with conventional design equipment and layout strategies. The comparison shows a reduction in area and power consumption by a factor of 2.5 and 3.7, respectively. The efficiency increases by a factor of at least nine. These results were proved by analog circuit simulations and test chip measurements.
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CMOS gate Array Architecture for digital signal processing applications
Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, 1Co-Authors: J.-m. Green, H. KlarAbstract:A CMOS gate Array Architecture for digital signal processing (DSP) is presented. The new structure takes into account the high degree of regularity of DSP datapaths and particularly supports the implementation of systolic Arrays in connection with a pipelining scheme of one addition per half clock cycle. This reduces both the area and the power consumption by about 21% and 33%, respectively, compared to conventional gate Arrays.
