The Experts below are selected from a list of 144 Experts worldwide ranked by ideXlab platform
T. Morie - One of the best experts on this subject based on the ideXlab platform.
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An Ultra-Wide Range Digitally Adaptive Control Phase Locked Loop with New 3-Phase Switched Capacitor Loop Filter
2006 Symposium on VLSI Circuits 2006. Digest of Technical Papers., 2006Co-Authors: S. Dosho, N. Yanagisawa, K. Sogawa, Y. Yamada, T. MorieAbstract:Recently, a frequency of the operating clock in microprocessors has been required to be changed frequently and widely in order to manage power consumption and throughput. Recently, the widest span of the input frequency has reached 640 times. Although the large Divider Ratio of the feedback Divider relaxes the variation by lowering the VCO gain, the variation of the charge pump current reaches 6400 times in using conventional methods. The new method moderates the variation by changing the gain of the VCO and the capacitance of the loop filter in addition to the charge pump current. Loop filters in the PLL have been evolving along with the improvement of adaptive-biased PLLs. Switched capacitor type loop filters (SC-LPFs) are tolerable to wide variation of the cutoff frequency and preferable for reducing the pattern jitter which appears remarkably on the PLL with high Divider Ratio. However, the conventional SC-LPF is slightly complex. Thus, the simple 3-phase SC-LPF which realizes the fully flat response has been developed
S. Dosho - One of the best experts on this subject based on the ideXlab platform.
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An Ultra-Wide Range Digitally Adaptive Control Phase Locked Loop with New 3-Phase Switched Capacitor Loop Filter
2006 Symposium on VLSI Circuits 2006. Digest of Technical Papers., 2006Co-Authors: S. Dosho, N. Yanagisawa, K. Sogawa, Y. Yamada, T. MorieAbstract:Recently, a frequency of the operating clock in microprocessors has been required to be changed frequently and widely in order to manage power consumption and throughput. Recently, the widest span of the input frequency has reached 640 times. Although the large Divider Ratio of the feedback Divider relaxes the variation by lowering the VCO gain, the variation of the charge pump current reaches 6400 times in using conventional methods. The new method moderates the variation by changing the gain of the VCO and the capacitance of the loop filter in addition to the charge pump current. Loop filters in the PLL have been evolving along with the improvement of adaptive-biased PLLs. Switched capacitor type loop filters (SC-LPFs) are tolerable to wide variation of the cutoff frequency and preferable for reducing the pattern jitter which appears remarkably on the PLL with high Divider Ratio. However, the conventional SC-LPF is slightly complex. Thus, the simple 3-phase SC-LPF which realizes the fully flat response has been developed
Anthony D. C. Macknight - One of the best experts on this subject based on the ideXlab platform.
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Application of membrane potential equations to tight epithelia
The Journal of Membrane Biology, 1991Co-Authors: Lyndsay G. M. Gordon, Anthony D. C. MacknightAbstract:It is shown that equations developed to analyze the contributions of secondary active transport processes to symmetrical cells (Gordon, L. G. M., Macknight, A. D. C., 1991, J. Membrane Biol. 120 : 139–152) can be used, with minor modifications, to analyze the steady-state membrane potential in epithelia under the unique situation of short circuiting. Only under such conditions is there a single intracellular potential relative to both the mucosal and serosal media. The equations are investigated in relation to a model tight epithelium—the toad urinary bladder. It is shown that the properties of the membrane transport pathways are such that the intracellular potential under short-circuit conditions must be more negative than often reported. Given measurements of membrane potential and of voltage-Divider Ratio, it is possible to use the equations to estimate the absolute values of the membrane permeabilities and conductances under shortcircuit conditions.
Che-wei Tien - One of the best experts on this subject based on the ideXlab platform.
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A Digital Phase-Locked Loop With Background Supply Voltage Sensitivity Minimization
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018Co-Authors: Che-wei TienAbstract:A digital phase-locked loop (DPLL) with the background supply voltage sensitivity minimization is presented. By using a frequency subtractor, a digital supply voltage sensitivity controller can suppress the supply voltage sensitivity of a DPLL. This DPLL is fabricated in 40-nm CMOS technology. Its active area is 0.006 mm2 where the supply voltage sensitivity controller occupies about 20%. The power consumption is 9.34 mW from a supply of 1.1 V wherein the supply voltage sensitivity controller consumes 840 μW. The output frequency of the DPLL is 5 GHz with a Divider Ratio of 64. The minimum measured supply voltage sensitivity is -0.0044[%-f VCO/%-VDD]. With a 50-mVPP, 100-kHz sinusoidal supply noise, the peak-topeak jitter is reduced from 41.48 to 23.15 ps, and the rms jitter is reduced from 7.26 to 3.47 ps.
A. Hajimiri - One of the best experts on this subject based on the ideXlab platform.
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Design of a novel low-power 4th-order 1.7 GHz CMOS frequency synthesizer for DCS-1800
2000 IEEE International Symposium on Circuits and Systems (ISCAS), 2000Co-Authors: A. Lehner, R. Weigel, D. Sewald, H. Eichfeld, A. HajimiriAbstract:A low-power fully-integrated type-2 4th-order 1.7 GHz CMOS frequency synthesizer for DCS-1800 application is designed and simulated in a 0.25 /spl mu/m process technology. The frequency switching is achieved using a novel architecture exploiting a direct digital synthesis (DDS) device as the frequency reference. The new topology significantly lowers the undesired sideband power due to Divider Ratio switching by directly shifting the frequency of the DDS reference. The frequency synthesizer (excluding the DDS device) dissipates only 9 mW of power from a 2 V power supply. It employs a fast-switching novel charge pump circuit and a low-noise fully-integrated differential LC voltage controlled oscillator using on-chip spiral inductors and accumulation-mode capacitors to meet the requirements of a DCS-1800 system. A detailed analysis of the phase noise in the 4th order loop is presented.