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Kazuhisa Haeiwa - One of the best experts on this subject based on the ideXlab platform.
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Sorter-Based Arithmetic Circuits for Sigma-Delta Domain Signal Processing—Part II: Multiplication and Algebraic Functions
IEEE Transactions on Circuits and Systems I: Regular Papers, 2012Co-Authors: Hisato Fujisaka, Takeshi Kamio, Masahiro Sakamoto, Kazuhisa HaeiwaAbstract:We construct arithmetic modules for Signal processing with sigma-delta modulated Signal form which has advantage in Signal quality over other pulsed Signal forms. In the second part of this paper, multi-input multipliers are presented first. Secondly, dividers and square root function modules with the multiplier on their internal feedback path are constructed. Combined use of the multipliers, dividers, and the square root functions creates various algebraic functions including polynomial and rational functions. Only two bit-manipulations, bit-permutation with sorting networks and bit-reversal with NOT gates, have built up all the algebraic operations on any form of SD modulated Signals. These modules, together with transcendental functions presented in the first part of this paper, organize an extensive module library for the sigma-delta Domain Signal processing. The multiplier output contains noise components which originate from quantization. The noise power can decrease in exchange for circuit complexity. A time-division multiplexing technique based on N-tone sigma-delta modulation is applied to the multipliers for reducing the complexity. Signal processing circuits built of nanometer-scale quantum effect devices must be equipped with fault tolerance of transient device error. By computer simulation of a multiplier built of single-electron tunneling devices, we found that the multiplier decreased its output SNDR from 43 to 27 dB at an OSR of 28 as the device error rate increased from 0 to 10-3. However, the multiplier was never functionally failed during the simulation.
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Sorter-Based Arithmetic Circuits for Sigma-Delta Domain Signal Processing—Part I: Addition, Approximate Transcendental Functions, and Log-Domain Operations
IEEE Transactions on Circuits and Systems I: Regular Papers, 2012Co-Authors: Hisato Fujisaka, Takeshi Kamio, Masahiro Sakamoto, Kazuhisa HaeiwaAbstract:We construct arithmetic modules for Signal processing with sigma-delta modulated Signal form which has advantage in Signal quality over other pulsed Signal forms. In the first part of this paper, adders and exponential function modules are presented first and secondly. By utilizing the two modules, several transcendental functions including hyperbolic and logarithmic functions are constructed. The exponential functions and logarithmic functions provide log-Domain arithmetic operations including multiplication, division, and power functions. Only two bit-manipulations, bit-permutation with sorting networks and bit-reversal with NOT gates, have built up all the arithmetic operations on any form of sigma-delta modulated Signals. These modules, together with algebraic functions to be presented in the second part of this paper, organize an extensive module library for the sigma-delta Domain Signal processing.
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Single-Electron Arithmetic Circuits for Sigma-Delta Domain Signal Processing
2008 8th IEEE Conference on Nanotechnology, 2008Co-Authors: Tsubasa Katao, Yoshinao Suzuki, Hisato Fujisaka, Takeshi Kamio, Kazuhisa HaeiwaAbstract:This paper presents single-electron arithmetic circuits for sigma-delta Domain Signal processing. Sigma-delta Domain Signal processing is one of hardware architectures which have tolerance for transient device errors. Results of circuit simulation show that the errors never trigger out-of-control state of the circuits and random surge of their outputs.
Keizo Kinoshita - One of the best experts on this subject based on the ideXlab platform.
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A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- Domain Signal processing
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014Co-Authors: Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo KinoshitaAbstract:A delay circuit using four-terminal magnetic-random-access-memory (MRAM) devices was designed for power-efficient time-Domain Signal processing. A cell area of 6.4 μm2 was obtained using 90-nm CMOS/MRAM technologies. The basic operations to both store the data and control the delay time were confirmed on the fabricated test chips. In addition, we proposed a power-efficient neuromorphic core using the delay circuit.
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ISCAS - A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- Domain Signal processing
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014Co-Authors: Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo KinoshitaAbstract:A delay circuit using four-terminal magnetic-random-access-memory (MRAM) devices was designed for power-efficient time-Domain Signal processing. A cell area of 6.4 μm 2 was obtained using 90-nm CMOS/MRAM technologies. The basic operations to both store the data and control the delay time were confirmed on the fabricated test chips. In addition, we proposed a power-efficient neuromorphic core using the delay circuit.
Hisato Fujisaka - One of the best experts on this subject based on the ideXlab platform.
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Sorter-Based Arithmetic Circuits for Sigma-Delta Domain Signal Processing—Part II: Multiplication and Algebraic Functions
IEEE Transactions on Circuits and Systems I: Regular Papers, 2012Co-Authors: Hisato Fujisaka, Takeshi Kamio, Masahiro Sakamoto, Kazuhisa HaeiwaAbstract:We construct arithmetic modules for Signal processing with sigma-delta modulated Signal form which has advantage in Signal quality over other pulsed Signal forms. In the second part of this paper, multi-input multipliers are presented first. Secondly, dividers and square root function modules with the multiplier on their internal feedback path are constructed. Combined use of the multipliers, dividers, and the square root functions creates various algebraic functions including polynomial and rational functions. Only two bit-manipulations, bit-permutation with sorting networks and bit-reversal with NOT gates, have built up all the algebraic operations on any form of SD modulated Signals. These modules, together with transcendental functions presented in the first part of this paper, organize an extensive module library for the sigma-delta Domain Signal processing. The multiplier output contains noise components which originate from quantization. The noise power can decrease in exchange for circuit complexity. A time-division multiplexing technique based on N-tone sigma-delta modulation is applied to the multipliers for reducing the complexity. Signal processing circuits built of nanometer-scale quantum effect devices must be equipped with fault tolerance of transient device error. By computer simulation of a multiplier built of single-electron tunneling devices, we found that the multiplier decreased its output SNDR from 43 to 27 dB at an OSR of 28 as the device error rate increased from 0 to 10-3. However, the multiplier was never functionally failed during the simulation.
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Sorter-Based Arithmetic Circuits for Sigma-Delta Domain Signal Processing—Part I: Addition, Approximate Transcendental Functions, and Log-Domain Operations
IEEE Transactions on Circuits and Systems I: Regular Papers, 2012Co-Authors: Hisato Fujisaka, Takeshi Kamio, Masahiro Sakamoto, Kazuhisa HaeiwaAbstract:We construct arithmetic modules for Signal processing with sigma-delta modulated Signal form which has advantage in Signal quality over other pulsed Signal forms. In the first part of this paper, adders and exponential function modules are presented first and secondly. By utilizing the two modules, several transcendental functions including hyperbolic and logarithmic functions are constructed. The exponential functions and logarithmic functions provide log-Domain arithmetic operations including multiplication, division, and power functions. Only two bit-manipulations, bit-permutation with sorting networks and bit-reversal with NOT gates, have built up all the arithmetic operations on any form of sigma-delta modulated Signals. These modules, together with algebraic functions to be presented in the second part of this paper, organize an extensive module library for the sigma-delta Domain Signal processing.
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Single-Electron Arithmetic Circuits for Sigma-Delta Domain Signal Processing
2008 8th IEEE Conference on Nanotechnology, 2008Co-Authors: Tsubasa Katao, Yoshinao Suzuki, Hisato Fujisaka, Takeshi Kamio, Kazuhisa HaeiwaAbstract:This paper presents single-electron arithmetic circuits for sigma-delta Domain Signal processing. Sigma-delta Domain Signal processing is one of hardware architectures which have tolerance for transient device errors. Results of circuit simulation show that the errors never trigger out-of-control state of the circuits and random surge of their outputs.
Ryusuke Nebashi - One of the best experts on this subject based on the ideXlab platform.
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A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- Domain Signal processing
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014Co-Authors: Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo KinoshitaAbstract:A delay circuit using four-terminal magnetic-random-access-memory (MRAM) devices was designed for power-efficient time-Domain Signal processing. A cell area of 6.4 μm2 was obtained using 90-nm CMOS/MRAM technologies. The basic operations to both store the data and control the delay time were confirmed on the fabricated test chips. In addition, we proposed a power-efficient neuromorphic core using the delay circuit.
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ISCAS - A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- Domain Signal processing
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014Co-Authors: Ryusuke Nebashi, Noboru Sakimura, Hiroaki Honjo, Ayuka Morioka, Yukihide Tsuji, Kunihiko Ishihara, Keiichi Tokutome, Sadahiko Miura, Shunsuke Fukami, Keizo KinoshitaAbstract:A delay circuit using four-terminal magnetic-random-access-memory (MRAM) devices was designed for power-efficient time-Domain Signal processing. A cell area of 6.4 μm 2 was obtained using 90-nm CMOS/MRAM technologies. The basic operations to both store the data and control the delay time were confirmed on the fabricated test chips. In addition, we proposed a power-efficient neuromorphic core using the delay circuit.
D. Python - One of the best experts on this subject based on the ideXlab platform.
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Low-voltage log-Domain Signal processing in CMOS and BiCMOS
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1999Co-Authors: M. Punzenberger, D. PythonAbstract:This paper presents the most important properties of log-Domain filters for the realization of low-voltage and low power analog Signal processing circuits. The noise behavior is discussed and the advantage of the combination of companding and class AB operation is highlighted. Examples of BiCMOS and CMOS realizations operating at supply voltages as low as 1 V are presented.
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Low-voltage log-Domain Signal processing in CMOS and BiCMOS
1997 IEEE International Symposium on Circuits and Systems (ISCAS), 1997Co-Authors: M. Punzenberger, D. PythonAbstract:This paper presents the most important properties of log-Domain filters for the realization of low-voltage (LV) and low-power (LP) analog Signal processing circuits. The noise behavior is briefly discussed and the advantage of the combination of companding and class AB operation is highlighted. Examples of BiCMOS and standard digital CMOS realizations operating at supply voltages as low as 1 V are presented.