The Experts below are selected from a list of 21651 Experts worldwide ranked by ideXlab platform

Dan Alexandrescu - One of the best experts on this subject based on the ideXlab platform.

  • Comprehensive Analysis of Sequential and Combinational Soft Errors in an Embedded Processor
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015
    Co-Authors: Mojtaba Ebrahimi, Adrian Evans, Mehdi B. Tahoori, Enrico Costenaro, Dan Alexandrescu, Vikas Chandra, Razi Seyyedi
    Abstract:

    Radiation-induced soft errors have become a key challenge in advanced commercial electronic components and systems. We present the results of a soft error rate (SER) analysis of an Embedded Processor. Our SER analysis platform accurately models generation, propagation, and masking effects starting from a technology response model derived using TCAD simulations at the device level all the way to application masking. The platform employs a combination of accurate models at the device level, analytical error propagation at gate level, and fault emulation at the architecture/application level to provide the detailed contribution of each component (flip-flops, combinational gates, and SRAMs) to the overall SER. At each stage in the modeling hierarchy, an appropriate level of abstraction is used to propagate the effect of errors to the next higher level. Unlike previous studies which are based on very simple test chips, analyzing the entire Processor gives more insight into the relative contributions of combinational and sequential SER. The results of this analysis can assist circuit designers to adopt effective hardening techniques to reduce the overall SER while meeting the required power and performance constraints.

  • comprehensive analysis of alpha and neutron particle induced soft errors in an Embedded Processor at nanoscales
    Design Automation and Test in Europe, 2014
    Co-Authors: Mojtaba Ebrahimi, Adrian Evans, Mehdi B. Tahoori, Enrico Costenaro, Razi Seyyedi, Dan Alexandrescu
    Abstract:

    Radiation-induced soft errors have become a key challenge in advanced commercial electronic components and systems. We present results of Soft Error Rate (SER) analysis of an Embedded Processor. Our SER analysis platform accurately models all generation, propagation and masking effects starting from a technology response model derived using TCAD simulations at the device level all the way to application masking. The platform employs a combination of empirical models at the device level, analytical error propagation at logic level and fault emulation at the architecture/application level to provide the detailed contribution of each component (flip-flops, combinational gates, and SRAMs) to the overall SER. At each stage in the modeling hierarchy, an appropriate level of abstraction is used to propagate the effect of errors to the next higher level. Unlike previous studies which are based on very simple test chips, analyzing the entire Processor gives more insight into the contributions of different components to the overall SER. The results of this analysis can assist circuit designers to adopt effective hardening techniques to reduce the overall SER while meeting required power and performance constraints.

  • DATE - Comprehensive analysis of alpha and neutron particle-induced soft errors in an Embedded Processor at nanoscales
    Design Automation & Test in Europe Conference & Exhibition (DATE) 2014, 2014
    Co-Authors: Mojtaba Ebrahimi, Adrian Evans, Mehdi B. Tahoori, Enrico Costenaro, Razi Seyyedi, Dan Alexandrescu
    Abstract:

    Radiation-induced soft errors have become a key challenge in advanced commercial electronic components and systems. We present results of Soft Error Rate (SER) analysis of an Embedded Processor. Our SER analysis platform accurately models all generation, propagation and masking effects starting from a technology response model derived using TCAD simulations at the device level all the way to application masking. The platform employs a combination of empirical models at the device level, analytical error propagation at logic level and fault emulation at the architecture/application level to provide the detailed contribution of each component (flip-flops, combinational gates, and SRAMs) to the overall SER. At each stage in the modeling hierarchy, an appropriate level of abstraction is used to propagate the effect of errors to the next higher level. Unlike previous studies which are based on very simple test chips, analyzing the entire Processor gives more insight into the contributions of different components to the overall SER. The results of this analysis can assist circuit designers to adopt effective hardening techniques to reduce the overall SER while meeting required power and performance constraints.

M. Matsui - One of the best experts on this subject based on the ideXlab platform.

  • ICCD - Design methodology and system for a configurable media Embedded Processor extensible to VLIW architecture
    Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2002
    Co-Authors: A. Mizuno, K. Kohno, R. Ohyama, T. Tokuyoshi, H. Uetani, H. Eichel, T. Miyamori, N. Matsumoto, M. Matsui
    Abstract:

    A new integrated system to design and generate a configurable Embedded Processor for multimedia applications has been developed. The system, "Media Embedded Processor Integrator", provides a distinctive feature that generates development tools, such as compilers and simulators, not only for the configurable Embedded Processor but also for its template based extensible VLIW co-Processor. This paper describes the architecture and the function of the "Media Embedded Processor Integrator" especially focusing on how the system treats the VLIW co-Processor extension. In order to determine an ISA for a 3-way VLIW co-Processor for image recognition as an example, several different sets of ISA were evaluated and compared for the best performance using corresponding compilers and simulators, which were generated by the system. The system greatly contributed to reduce this entire ISA definition process.

  • Design methodology and system for a configurable media Embedded Processor extensible to VLIW architecture
    Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2002
    Co-Authors: A. Mizuno, K. Kohno, R. Ohyama, T. Tokuyoshi, H. Uetani, H. Eichel, T. Miyamori, N. Matsumoto, M. Matsui
    Abstract:

    A new integrated system to design and generate a configurable Embedded Processor for multimedia applications has been developed. The system, "Media Embedded Processor Integrator", provides a distinctive feature that generates development tools, such as compilers and simulators, not only for the configurable Embedded Processor but also for its template based extensible VLIW co-Processor. This paper describes the architecture and the function of the "Media Embedded Processor Integrator" especially focusing on how the system treats the VLIW co-Processor extension. In order to determine an ISA for a 3-way VLIW co-Processor for image recognition as an example, several different sets of ISA were evaluated and compared for the best performance using corresponding compilers and simulators, which were generated by the system. The system greatly contributed to reduce this entire ISA definition process.

Mojtaba Ebrahimi - One of the best experts on this subject based on the ideXlab platform.

  • Comprehensive Analysis of Sequential and Combinational Soft Errors in an Embedded Processor
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015
    Co-Authors: Mojtaba Ebrahimi, Adrian Evans, Mehdi B. Tahoori, Enrico Costenaro, Dan Alexandrescu, Vikas Chandra, Razi Seyyedi
    Abstract:

    Radiation-induced soft errors have become a key challenge in advanced commercial electronic components and systems. We present the results of a soft error rate (SER) analysis of an Embedded Processor. Our SER analysis platform accurately models generation, propagation, and masking effects starting from a technology response model derived using TCAD simulations at the device level all the way to application masking. The platform employs a combination of accurate models at the device level, analytical error propagation at gate level, and fault emulation at the architecture/application level to provide the detailed contribution of each component (flip-flops, combinational gates, and SRAMs) to the overall SER. At each stage in the modeling hierarchy, an appropriate level of abstraction is used to propagate the effect of errors to the next higher level. Unlike previous studies which are based on very simple test chips, analyzing the entire Processor gives more insight into the relative contributions of combinational and sequential SER. The results of this analysis can assist circuit designers to adopt effective hardening techniques to reduce the overall SER while meeting the required power and performance constraints.

  • comprehensive analysis of alpha and neutron particle induced soft errors in an Embedded Processor at nanoscales
    Design Automation and Test in Europe, 2014
    Co-Authors: Mojtaba Ebrahimi, Adrian Evans, Mehdi B. Tahoori, Enrico Costenaro, Razi Seyyedi, Dan Alexandrescu
    Abstract:

    Radiation-induced soft errors have become a key challenge in advanced commercial electronic components and systems. We present results of Soft Error Rate (SER) analysis of an Embedded Processor. Our SER analysis platform accurately models all generation, propagation and masking effects starting from a technology response model derived using TCAD simulations at the device level all the way to application masking. The platform employs a combination of empirical models at the device level, analytical error propagation at logic level and fault emulation at the architecture/application level to provide the detailed contribution of each component (flip-flops, combinational gates, and SRAMs) to the overall SER. At each stage in the modeling hierarchy, an appropriate level of abstraction is used to propagate the effect of errors to the next higher level. Unlike previous studies which are based on very simple test chips, analyzing the entire Processor gives more insight into the contributions of different components to the overall SER. The results of this analysis can assist circuit designers to adopt effective hardening techniques to reduce the overall SER while meeting required power and performance constraints.

  • DATE - Comprehensive analysis of alpha and neutron particle-induced soft errors in an Embedded Processor at nanoscales
    Design Automation & Test in Europe Conference & Exhibition (DATE) 2014, 2014
    Co-Authors: Mojtaba Ebrahimi, Adrian Evans, Mehdi B. Tahoori, Enrico Costenaro, Razi Seyyedi, Dan Alexandrescu
    Abstract:

    Radiation-induced soft errors have become a key challenge in advanced commercial electronic components and systems. We present results of Soft Error Rate (SER) analysis of an Embedded Processor. Our SER analysis platform accurately models all generation, propagation and masking effects starting from a technology response model derived using TCAD simulations at the device level all the way to application masking. The platform employs a combination of empirical models at the device level, analytical error propagation at logic level and fault emulation at the architecture/application level to provide the detailed contribution of each component (flip-flops, combinational gates, and SRAMs) to the overall SER. At each stage in the modeling hierarchy, an appropriate level of abstraction is used to propagate the effect of errors to the next higher level. Unlike previous studies which are based on very simple test chips, analyzing the entire Processor gives more insight into the contributions of different components to the overall SER. The results of this analysis can assist circuit designers to adopt effective hardening techniques to reduce the overall SER while meeting required power and performance constraints.

Tung Thanh Hoang - One of the best experts on this subject based on the ideXlab platform.

  • Customization for an Energy-Efficient Embedded Processor with Flexible Datapath
    2020
    Co-Authors: Tung Thanh Hoang
    Abstract:

    Due to diversified demands of customers, Embedded Processor datapaths have been extended to accept many functional units, thus growing more complex and energy inefficient. For this reason, it is necessary to carefully analyze the characteristics of the specific Embedded applications and fine-tune the hardware implementation. This thesis addresses two approaches to the design of an energy-efficient Embedded Processor with flexible datapaths (FlexCore): The first approach entails customizing the Processor by considering data-routing flexibility between datapath units, while the second one deals with integration of accelerators for performance enhancement. The first part of the thesis focuses on a Processor design environment that allows for customization of the FlexCore Processor. Here, a design space exploration methodology to customize the FlexCore datapath interconnect to a domain of applications, with the goal of reducing energy dissipation, is proposed. The second part of the thesis proposes a high-speed energy-efficient 2-cycle multiply-accumulate architecture, which can act as an accelerator for Embedded Processors. As an extension to the proposed architecture, a versatile double throughput multiply-accumulate unit for data-intensive computations is proposed. The third part of the thesis deals with a design flow to systematically integrate accelerators into an Embedded Processor with flexible datapath for performance enhancement. By taking advantage of high-throughput processing, the integrated FlexCore-DTMAC architecture shows a significant improvement in both execution time and energy dissipation. Finally, in addition to the novel solutions for customization of an energy-efficient Embedded Processor with flexible datapath, some future works are also discussed in the framework of this thesis.

  • Viterbi Accelerator for Embedded Processor Datapaths
    2012 IEEE 23rd International Conference on Application-Specific Systems Architectures and Processors, 2012
    Co-Authors: Muhammad Waqar Azhar, Tung Thanh Hoang, Magnus Själander, Akshay Vijayashekar, Kashan Khurshid Ansari, Per Larsson-edefors
    Abstract:

    We present a novel architecture for a lightweight Viterbi accelerator that can be tightly integrated inside an Embedded Processor datapath. We investigate the accelerator's impact on Processor performance by using the EEMBC Viterbi benchmark and the in-house Viterbi Branch Metric kernel. Our evaluation based on the EEMBC benchmark shows that an accelerated 65-nm 2.7-ns Processor datapath is 20% larger but 90% more cycle efficient than a datapath lacking the Viterbi accelerator, leading to an 87% overall energy reduction and a data throughput of 3.52 Mbit/s.

  • Power gating multiplier of Embedded Processor datapath
    2011 7th Conference on Ph.D. Research in Microelectronics and Electronics, 2011
    Co-Authors: Tung Thanh Hoang, Vineeth Saseendran, Donatas Siaudinis, Per Larsson-edefors
    Abstract:

    Leakage power is an important concern in modern electronic designs. To efficiently employ power gating for leakage reduction in Embedded Processors, the architecture must provide a clear-cut software support for power gating and the power-gated unit must have significant idle times during the execution of the applications. We introduce power gating of individual datapath units for the Embedded architecture of FlexCore, to evaluate if leakage reductions in temporarily idle units can reduce the overall power dissipation of compute-intensive applications. Post-layout multi-corner simulations for a 65-nm FlexCore datapath implementation demonstrate that power gating of the multiplier unit yields overall datapath energy savings, up to 14%, for two EEMBC benchmarks.

  • design space exploration for an Embedded Processor with flexible datapath interconnect
    Application-Specific Systems Architectures and Processors, 2010
    Co-Authors: Tung Thanh Hoang, Magnus Själander, Ulf Jalmbrant, Erik Der Hagopian, Kasyab P Subramaniyan, Per Larssonedefors
    Abstract:

    The design of an Embedded Processor is dependent on the application domain. Traditionally, design solutions specific to an application domain have been available in three forms: VLIW-based DSP Processors, ASICs and FPGAs; each respectively offering generality of application domain, energy efficiency and flexibility. However, while matching the application domain to the resources needed, the design space becomes huge. We present FlexTools, a tool framework built around the FlexCore architecture to evaluate performance and energy efficiency for different applications. Here we demonstrate FlexTools for design space exploration with a focus on the data-routing flexibility of the FlexCore Processor, in search of energy-efficient interconnect configurations that are both cycle-count and hardware efficient. Evaluation results suggest that a well-optimized instance of a 65-nm multiplier-extended FlexCore Processor datapath, obtained using FlexTools, executes nine integer EEMBC benchmarks with a 15% cycle count reduction and dissipates 17% less energy than a reference MIPS datapath.

Enrico Costenaro - One of the best experts on this subject based on the ideXlab platform.

  • Comprehensive Analysis of Sequential and Combinational Soft Errors in an Embedded Processor
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2015
    Co-Authors: Mojtaba Ebrahimi, Adrian Evans, Mehdi B. Tahoori, Enrico Costenaro, Dan Alexandrescu, Vikas Chandra, Razi Seyyedi
    Abstract:

    Radiation-induced soft errors have become a key challenge in advanced commercial electronic components and systems. We present the results of a soft error rate (SER) analysis of an Embedded Processor. Our SER analysis platform accurately models generation, propagation, and masking effects starting from a technology response model derived using TCAD simulations at the device level all the way to application masking. The platform employs a combination of accurate models at the device level, analytical error propagation at gate level, and fault emulation at the architecture/application level to provide the detailed contribution of each component (flip-flops, combinational gates, and SRAMs) to the overall SER. At each stage in the modeling hierarchy, an appropriate level of abstraction is used to propagate the effect of errors to the next higher level. Unlike previous studies which are based on very simple test chips, analyzing the entire Processor gives more insight into the relative contributions of combinational and sequential SER. The results of this analysis can assist circuit designers to adopt effective hardening techniques to reduce the overall SER while meeting the required power and performance constraints.

  • comprehensive analysis of alpha and neutron particle induced soft errors in an Embedded Processor at nanoscales
    Design Automation and Test in Europe, 2014
    Co-Authors: Mojtaba Ebrahimi, Adrian Evans, Mehdi B. Tahoori, Enrico Costenaro, Razi Seyyedi, Dan Alexandrescu
    Abstract:

    Radiation-induced soft errors have become a key challenge in advanced commercial electronic components and systems. We present results of Soft Error Rate (SER) analysis of an Embedded Processor. Our SER analysis platform accurately models all generation, propagation and masking effects starting from a technology response model derived using TCAD simulations at the device level all the way to application masking. The platform employs a combination of empirical models at the device level, analytical error propagation at logic level and fault emulation at the architecture/application level to provide the detailed contribution of each component (flip-flops, combinational gates, and SRAMs) to the overall SER. At each stage in the modeling hierarchy, an appropriate level of abstraction is used to propagate the effect of errors to the next higher level. Unlike previous studies which are based on very simple test chips, analyzing the entire Processor gives more insight into the contributions of different components to the overall SER. The results of this analysis can assist circuit designers to adopt effective hardening techniques to reduce the overall SER while meeting required power and performance constraints.

  • DATE - Comprehensive analysis of alpha and neutron particle-induced soft errors in an Embedded Processor at nanoscales
    Design Automation & Test in Europe Conference & Exhibition (DATE) 2014, 2014
    Co-Authors: Mojtaba Ebrahimi, Adrian Evans, Mehdi B. Tahoori, Enrico Costenaro, Razi Seyyedi, Dan Alexandrescu
    Abstract:

    Radiation-induced soft errors have become a key challenge in advanced commercial electronic components and systems. We present results of Soft Error Rate (SER) analysis of an Embedded Processor. Our SER analysis platform accurately models all generation, propagation and masking effects starting from a technology response model derived using TCAD simulations at the device level all the way to application masking. The platform employs a combination of empirical models at the device level, analytical error propagation at logic level and fault emulation at the architecture/application level to provide the detailed contribution of each component (flip-flops, combinational gates, and SRAMs) to the overall SER. At each stage in the modeling hierarchy, an appropriate level of abstraction is used to propagate the effect of errors to the next higher level. Unlike previous studies which are based on very simple test chips, analyzing the entire Processor gives more insight into the contributions of different components to the overall SER. The results of this analysis can assist circuit designers to adopt effective hardening techniques to reduce the overall SER while meeting required power and performance constraints.