The Experts below are selected from a list of 44085 Experts worldwide ranked by ideXlab platform

Dennis Sylvester - One of the best experts on this subject based on the ideXlab platform.

  • a 110 nw resistive frequency locked on chip oscillator with 34 3 ppm c temperature stability for system on chip designs
    IEEE Journal of Solid-state Circuits, 2016
    Co-Authors: Myungjoon Choi, Taekwang Jang, Suyoung Bang, Yao Shi, David Blaauw, Dennis Sylvester
    Abstract:

    This work presents a sub- $\mu \text {W}$ on-chip oscillator for fully integrated system-on-chip designs. The proposed oscillator introduces a resistive frequency locked loop topology for accurate clock generation. In this topology, a switched-capacitor circuit is controlled by an internal voltage-controlled oscillator (VCO), and the Equivalent Resistance of this switched-capacitor is matched to a temperature-compensated on-chip resistor using an ultra-low power amplifier. This design yields a temperature-compensated frequency from the internal VCO. The approach eliminates the traditional comparator from the oscillation loop; this comparator typically consumes a significant portion of the total oscillator power and limits temperature stability in conventional RC relaxation oscillators due to its temperature-dependent delay. A test chip is fabricated in $0.18~\mu \text {m}$ CMOS that exhibits a temperature coefficient of 34.3 ppm/°C with long-term stability of less than 7 ppm (12 second integration time) while consuming 110 nW at 70.4 kHz. A radio transmitter circuit that uses the proposed oscillator as a baseband timing source is also presented to demonstrate a system-on-chip design using this oscillator.

  • a 99nw 70 4khz resistive frequency locking on chip oscillator with 27 4ppm oc temperature stability
    Symposium on VLSI Circuits, 2015
    Co-Authors: Myungjoon Choi, Taekwang Jang, Suyoung Bang, David Blaauw, Dennis Sylvester
    Abstract:

    We present a low power on-chip oscillator for system-on-chip designs. The oscillator introduces a resistive frequency locking loop topology where the Equivalent Resistance of a switched-capacitor is matched to a temperature-compensated resistor. The approach eliminates the traditional comparator from the oscillation loop, which consumes significant power and limits temperature stability in conventional relaxation oscillators. The oscillator is fabricated in 0.18μm CMOS and exhibits 27.4ppm/oC and <7ppm long-term stability while consuming 99.4nW at 70.4 kHz.

Yajun Ha - One of the best experts on this subject based on the ideXlab platform.

  • statistical noise margin estimation for sub threshold combinational circuits
    Asia and South Pacific Design Automation Conference, 2008
    Co-Authors: Yu Pu, José Pineda De Gyvez, Henk Corporaal, Yajun Ha
    Abstract:

    The increasingly popular sub-threshold design is strongly calling for EDA support to estimate noise margins, minimum functional supply voltage, as well as the functional yield. In this paper, we propose a fast, accurate and statistical approach to accomplish these goals. First, we derive close-form functions based on a new Equivalent Resistance model which enables the fast estimation of noise margins of individual cells at the gate-level. Second, we propose to calculate and propagate the noise margin information with an affine arithmetic model that takes into account process variations and correspondent inter-cell correlations. Experiments with ISCAS benchmarks have shown that the new approach has an accuracy of 98.5% w.r.t. transistor-level Monte Carlo simulations. The running time per input vector of the new approach only needs a few seconds, in contrast to the many hours required by transistor-level DC Monte-Carlo simulations. To the best of our knowledge, we are the first to provide a fast, accurate and statistical methodology other than Monte-Carlo simulation for the noise margin estimation of sub-threshold combinational circuits.

  • statistical noise margin estimation for sub threshold combinational circuits
    Asia and South Pacific Design Automation Conference, 2008
    Co-Authors: Yu Pu, José Pineda De Gyvez, Henk Corporaal, Yajun Ha
    Abstract:

    The increasingly popular sub-threshold design is strongly calling for EDA support to estimate noise margins, minimum functional supply voltage, as well as the functional yield. In this paper, we propose a fast, accurate and statistical approach to accomplish these goals. First, we derive close-form functions based on a new Equivalent Resistance model which enables the fast estimation of noise margins of individual cells at the gate-level. Second, we propose to calculate and propagate the noise margin information with an affine arithmetic model that takes into account process variations and correspondent inter-cell correlations. Experiments with ISCAS benchmarks have shown that the new approach has an accuracy of 98.5% w.r.t. transistor-level Monte Carlo simulations. The running time per input vector of the new approach only needs a few seconds, in contrast to the many hours required by transistor-level DC Monte-Carlo simulations. To the best of our knowledge, we are the first to provide a fast, accurate and statistical methodology other than Monte-Carlo simulation for the noise margin estimation of sub-threshold combinational circuits.

Myungjoon Choi - One of the best experts on this subject based on the ideXlab platform.

  • a 110 nw resistive frequency locked on chip oscillator with 34 3 ppm c temperature stability for system on chip designs
    IEEE Journal of Solid-state Circuits, 2016
    Co-Authors: Myungjoon Choi, Taekwang Jang, Suyoung Bang, Yao Shi, David Blaauw, Dennis Sylvester
    Abstract:

    This work presents a sub- $\mu \text {W}$ on-chip oscillator for fully integrated system-on-chip designs. The proposed oscillator introduces a resistive frequency locked loop topology for accurate clock generation. In this topology, a switched-capacitor circuit is controlled by an internal voltage-controlled oscillator (VCO), and the Equivalent Resistance of this switched-capacitor is matched to a temperature-compensated on-chip resistor using an ultra-low power amplifier. This design yields a temperature-compensated frequency from the internal VCO. The approach eliminates the traditional comparator from the oscillation loop; this comparator typically consumes a significant portion of the total oscillator power and limits temperature stability in conventional RC relaxation oscillators due to its temperature-dependent delay. A test chip is fabricated in $0.18~\mu \text {m}$ CMOS that exhibits a temperature coefficient of 34.3 ppm/°C with long-term stability of less than 7 ppm (12 second integration time) while consuming 110 nW at 70.4 kHz. A radio transmitter circuit that uses the proposed oscillator as a baseband timing source is also presented to demonstrate a system-on-chip design using this oscillator.

  • a 99nw 70 4khz resistive frequency locking on chip oscillator with 27 4ppm oc temperature stability
    Symposium on VLSI Circuits, 2015
    Co-Authors: Myungjoon Choi, Taekwang Jang, Suyoung Bang, David Blaauw, Dennis Sylvester
    Abstract:

    We present a low power on-chip oscillator for system-on-chip designs. The oscillator introduces a resistive frequency locking loop topology where the Equivalent Resistance of a switched-capacitor is matched to a temperature-compensated resistor. The approach eliminates the traditional comparator from the oscillation loop, which consumes significant power and limits temperature stability in conventional relaxation oscillators. The oscillator is fabricated in 0.18μm CMOS and exhibits 27.4ppm/oC and <7ppm long-term stability while consuming 99.4nW at 70.4 kHz.

Yu Pu - One of the best experts on this subject based on the ideXlab platform.

  • statistical noise margin estimation for sub threshold combinational circuits
    Asia and South Pacific Design Automation Conference, 2008
    Co-Authors: Yu Pu, José Pineda De Gyvez, Henk Corporaal, Yajun Ha
    Abstract:

    The increasingly popular sub-threshold design is strongly calling for EDA support to estimate noise margins, minimum functional supply voltage, as well as the functional yield. In this paper, we propose a fast, accurate and statistical approach to accomplish these goals. First, we derive close-form functions based on a new Equivalent Resistance model which enables the fast estimation of noise margins of individual cells at the gate-level. Second, we propose to calculate and propagate the noise margin information with an affine arithmetic model that takes into account process variations and correspondent inter-cell correlations. Experiments with ISCAS benchmarks have shown that the new approach has an accuracy of 98.5% w.r.t. transistor-level Monte Carlo simulations. The running time per input vector of the new approach only needs a few seconds, in contrast to the many hours required by transistor-level DC Monte-Carlo simulations. To the best of our knowledge, we are the first to provide a fast, accurate and statistical methodology other than Monte-Carlo simulation for the noise margin estimation of sub-threshold combinational circuits.

  • statistical noise margin estimation for sub threshold combinational circuits
    Asia and South Pacific Design Automation Conference, 2008
    Co-Authors: Yu Pu, José Pineda De Gyvez, Henk Corporaal, Yajun Ha
    Abstract:

    The increasingly popular sub-threshold design is strongly calling for EDA support to estimate noise margins, minimum functional supply voltage, as well as the functional yield. In this paper, we propose a fast, accurate and statistical approach to accomplish these goals. First, we derive close-form functions based on a new Equivalent Resistance model which enables the fast estimation of noise margins of individual cells at the gate-level. Second, we propose to calculate and propagate the noise margin information with an affine arithmetic model that takes into account process variations and correspondent inter-cell correlations. Experiments with ISCAS benchmarks have shown that the new approach has an accuracy of 98.5% w.r.t. transistor-level Monte Carlo simulations. The running time per input vector of the new approach only needs a few seconds, in contrast to the many hours required by transistor-level DC Monte-Carlo simulations. To the best of our knowledge, we are the first to provide a fast, accurate and statistical methodology other than Monte-Carlo simulation for the noise margin estimation of sub-threshold combinational circuits.

Zhi-zhong Tan - One of the best experts on this subject based on the ideXlab platform.

  • a fractional order multifunctional n step honeycomb rlc circuit network
    Journal of Zhejiang University Science C, 2017
    Co-Authors: Ling Zhou, Zhi-zhong Tan, Qinghua Zhang
    Abstract:

    We investigate a multifunctional n-step honeycomb network which has not been studied before. By adjusting the circuit parameters, such a network can be transformed into several different networks with a variety of functions, such as a regular ladder network and a triangular network. We derive two new formulae for Equivalent Resistance in the resistor network and Equivalent impedance in the LC network, which are in the fractional-order domain. First, we simplify the complex network into a simple Equivalent model. Second, using Kirchhoff’s laws, we establish a fractional difference equation. Third, we construct an Equivalent transformation method to obtain a general solution for the nonlinear differential equation. In practical applications, several interesting special results are obtained. In particular, an n-step impedance LC network is discussed and many new characteristics of complex impedance have been found.

  • theory on Resistance of m n cobweb network and its application
    International Journal of Circuit Theory and Applications, 2015
    Co-Authors: Zhi-zhong Tan
    Abstract:

    A basic theorem of Equivalent Resistance between two arbitrary nodes in an m×n cobweb network in both finite and infinite conditions is discovered, and two conjectures on the Equivalent Resistance are proved in terms of the basic theorem. We built a tridiagonal matrix equation by means of network analysis and made a diagonalization method of matrix transformation and work out its explicit expressions. The new formulae obtained here can be effectively applied in complex impedance network, especially the formulation leads to the occurrence of resonances and a series of novel results in RLC denote resistor, inductance and capacitance network. These curious results suggest the possibility of practical applications to resonant circuits. Copyright © 2014 John Wiley & Sons, Ltd.

  • Recursion-transform method for computing Resistance of the complex resistor network with three arbitrary boundaries.
    Physical review. E Statistical nonlinear and soft matter physics, 2015
    Co-Authors: Zhi-zhong Tan
    Abstract:

    We develop a general recursion-transform (R-T) method for a two-dimensional resistor network with a zero resistor boundary. As applications of the R-T method, we consider a significant example to illuminate the usefulness for calculating Resistance of a rectangular $m\ifmmode\times\else\texttimes\fi{}n$ resistor network with a null resistor and three arbitrary boundaries, a problem never solved before, since Green's function techniques and Laplacian matrix approaches are invalid in this case. Looking for the exact calculation of the Resistance of a binary resistor network is important but difficult in the case of an arbitrary boundary since the boundary is like a wall or trap which affects the behavior of finite network. In this paper we obtain several general formulas of Resistance between any two nodes in a nonregular $m\ifmmode\times\else\texttimes\fi{}n$ resistor network in both finite and infinite cases. In particular, 12 special cases are given by reducing one of the general formulas to understand its applications and meanings, and an integral identity is found when we compare the Equivalent Resistance of two different structures of the same problem in a resistor network.

  • Resistance and capacitance of 4 n cobweb network and two conjectures
    International Journal of Circuit Theory and Applications, 2015
    Co-Authors: Zhi-zhong Tan, Ling Zhou, Dafeng Luo
    Abstract:

    A classic problem in electric circuit theory studied by numerous authors over 160 years is the computation of the Resistance between two nodes in a resistor network, yet some basic problem in m×n cobweb network is still not solved ideally. The Equivalent Resistance and capacitance of 4×n cobweb network are investigated in this paper. We built a quaternion matrix equation and proposed the method of matrix transformations in terms of the network analysis. We proposed a brief Equivalent Resistance formula and find that the Equivalent Resistance is expressed by coskπ/9 in a series of strict calculation. Meanwhile, an Equivalent Resistance of infinite networks is gained. Using the inverse mapping relation between capacitance parameters and Resistance parameters, the Equivalent capacitance formula is also given for the 4×n capacitance cobweb network. By analyzing and comparing the Equivalent Resistances of the 1×n, 2×n, 3×n and 4×n cobweb networks, two conjectures on the Equivalent Resistance and capacitance of the m×n cobweb network are proposed. Copyright © 2013 John Wiley & Sons, Ltd.

  • the Equivalent Resistance of a 3 n cobweb network and its conjecture of an m n cobweb network
    Journal of Physics A, 2013
    Co-Authors: Zhi-zhong Tan, Ling Zhou, Jianhua Yang
    Abstract:

    We investigate the Equivalent Resistance of a 3 × n cobweb network. The difference equations of the model are constructed by network analysis and their general solution is obtained by matrix transformations. It is found that the Equivalent Resistance can be expressed by the trigonometric function of kπ/7, which decreases with the increase of the order n. By analyzing and comparing the Equivalent Resistances of the 1 × n, 2 × n and 3 × n cobweb networks, a conjecture on the Equivalent Resistance of the m × n cobweb network is proposed.