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Chenchang Zhan - One of the best experts on this subject based on the ideXlab platform.

  • a 0 035mm2 150ma fast response low dropout regulator based on matching enhanced Error Amplifier and multi threshold controlled unity gain buffer in 0 13μm cmos
    International Symposium on Circuits and Systems, 2016
    Co-Authors: Chenchang Zhan, Winghung Ki, Jiawei Zheng
    Abstract:

    A low-dropout regulator (LDR) using a matching-enhanced Error Amplifier (ME-EA) and a multi-threshold-controlled unity-gain buffer (MTC-UGB) is proposed in this work. With the majority of transistors being high-voltage devices of the process, the regulator tolerates a high in put voltage range, which alleviates the reliability concern caused by low-voltage transistors. The ME-EA allows for tight line and load regulations. The MTC-UGB, by using low-voltage input transistors with locally regulated terminal voltage, enables large loop bandwidth and fast load transient responses without using compensation capacitor or large ESR of the output capacitor for compensation. Fabricated in a 0.13μm CMOS process, the proposed LDR occupies 0.035 mm2 of active area and consumes 18 μA of quiescent current and achieves 6 mV of voltage dip for 150 mA of load transient.

  • ISCAS - A 0.035mm2 150mA fast-response low-dropout regulator based on matching-enhanced Error Amplifier and multi-threshold-controlled unity-gain buffer in 0.13μm CMOS
    2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016
    Co-Authors: Chenchang Zhan, Jiawei Zheng, Yonggen Liu
    Abstract:

    A low-dropout regulator (LDR) using a matching-enhanced Error Amplifier (ME-EA) and a multi-threshold-controlled unity-gain buffer (MTC-UGB) is proposed in this work. With the majority of transistors being high-voltage devices of the process, the regulator tolerates a high in put voltage range, which alleviates the reliability concern caused by low-voltage transistors. The ME-EA allows for tight line and load regulations. The MTC-UGB, by using low-voltage input transistors with locally regulated terminal voltage, enables large loop bandwidth and fast load transient responses without using compensation capacitor or large ESR of the output capacitor for compensation. Fabricated in a 0.13μm CMOS process, the proposed LDR occupies 0.035 mm2 of active area and consumes 18 μA of quiescent current and achieves 6 mV of voltage dip for 150 mA of load transient.

  • ISCAS - Fast-transient-response high-PSR low-dropout regulator based on ultra-fast Error Amplifier and unity-gain buffer for portable applications
    2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014
    Co-Authors: Yonggen Liu, Chenchang Zhan
    Abstract:

    A low-dropout regulator (LDR) using an ultra-fast Error Amplifier (EA) and ultra-fast unity-gain buffer (UGB) is proposed in this paper. By inserting a UGB between the EA and the inverting second stage, the non-dominant poles are pushed to high frequencies to achieve large loading capability and wide loop bandwidth with good stability. High power supply rejection (PSR) up to very high frequencies is hence achieved. Moreover, transient-enhancement techniques employed by the EA and UGB enable very fast load transient responses. The proposed LDR was designed in a 0.13μm mixed-mode CMOS process. Simulation results show that the quiescent current is 4μA and it achieves 7mV voltage dip for a load current step of 400mA with 1ns edge times. The PSR for all load range are better than -28dB at 10MHz and -9dB at 50MHz, respectively.

Yathei Lam - One of the best experts on this subject based on the ideXlab platform.

  • near threshold startup integrated boost converter with slew rate enhanced Error Amplifier
    International Symposium on Circuits and Systems, 2009
    Co-Authors: Yatto Wong, Homing Wan, Kwokkuen Kwong, Yathei Lam
    Abstract:

    An integrated voltage-mode boost converter that starts up at 0.9V is successfully implemented in a standard 3.3/5V 0.6µm CMOS process with V tn =0.7V and |V tp |=0.8V. The special features are: (1) a near-threshold soft-start circuit that keeps maximum in-rush current under control; (2) a slew rate enhanced Error Amplifier that achieves stable response over a wide range of supply voltage; and (3) a capacitor multiplier in implementing the compensation capacitor that reduces die area. Maximum efficiency of 93% is achieved at an output power of 260mW.

  • ISCAS - Near-threshold startup integrated boost converter with slew rate enhanced Error Amplifier
    2009 IEEE International Symposium on Circuits and Systems, 2009
    Co-Authors: Yatto Wong, Homing Wan, Kwokkuen Kwong, Yathei Lam
    Abstract:

    An integrated voltage-mode boost converter that starts up at 0.9V is successfully implemented in a standard 3.3/5V 0.6µm CMOS process with V tn =0.7V and |V tp |=0.8V. The special features are: (1) a near-threshold soft-start circuit that keeps maximum in-rush current under control; (2) a slew rate enhanced Error Amplifier that achieves stable response over a wide range of supply voltage; and (3) a capacitor multiplier in implementing the compensation capacitor that reduces die area. Maximum efficiency of 93% is achieved at an output power of 260mW.

Yonggen Liu - One of the best experts on this subject based on the ideXlab platform.

  • ISCAS - A 0.035mm2 150mA fast-response low-dropout regulator based on matching-enhanced Error Amplifier and multi-threshold-controlled unity-gain buffer in 0.13μm CMOS
    2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016
    Co-Authors: Chenchang Zhan, Jiawei Zheng, Yonggen Liu
    Abstract:

    A low-dropout regulator (LDR) using a matching-enhanced Error Amplifier (ME-EA) and a multi-threshold-controlled unity-gain buffer (MTC-UGB) is proposed in this work. With the majority of transistors being high-voltage devices of the process, the regulator tolerates a high in put voltage range, which alleviates the reliability concern caused by low-voltage transistors. The ME-EA allows for tight line and load regulations. The MTC-UGB, by using low-voltage input transistors with locally regulated terminal voltage, enables large loop bandwidth and fast load transient responses without using compensation capacitor or large ESR of the output capacitor for compensation. Fabricated in a 0.13μm CMOS process, the proposed LDR occupies 0.035 mm2 of active area and consumes 18 μA of quiescent current and achieves 6 mV of voltage dip for 150 mA of load transient.

  • ISCAS - Fast-transient-response high-PSR low-dropout regulator based on ultra-fast Error Amplifier and unity-gain buffer for portable applications
    2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014
    Co-Authors: Yonggen Liu, Chenchang Zhan
    Abstract:

    A low-dropout regulator (LDR) using an ultra-fast Error Amplifier (EA) and ultra-fast unity-gain buffer (UGB) is proposed in this paper. By inserting a UGB between the EA and the inverting second stage, the non-dominant poles are pushed to high frequencies to achieve large loading capability and wide loop bandwidth with good stability. High power supply rejection (PSR) up to very high frequencies is hence achieved. Moreover, transient-enhancement techniques employed by the EA and UGB enable very fast load transient responses. The proposed LDR was designed in a 0.13μm mixed-mode CMOS process. Simulation results show that the quiescent current is 4μA and it achieves 7mV voltage dip for a load current step of 400mA with 1ns edge times. The PSR for all load range are better than -28dB at 10MHz and -9dB at 50MHz, respectively.

Bo Zhang - One of the best experts on this subject based on the ideXlab platform.

  • An Error Amplifier With a Low Power Multi-Mode Voltage Clamper for Transient Enhancement and High Reliability
    IEEE Transactions on Circuits and Systems I: Regular Papers, 2020
    Co-Authors: Zekun Zhou, Wang Anqi, Wang Yunkun, Wang Jiani, Shi Yue, Zhuo Wang, Bo Zhang
    Abstract:

    This paper proposes a low power area-efficient multi-mode voltage clamper circuit called pseudo differential pair and applies it into an Error Amplifier (EA) which can be used in DC-DC converters as a practical design example. In addition to a normal amplifying mode, the Error Amplifier has two extra operation modes with the help of the voltage clamper, which can limit the maximum output voltage and the maximum sink current, respectively. By inserting this pseudo differential pair of only three transistors in the intermediate stage of the Amplifier, a voltage-current feedback is introduced to achieve the voltage limiting function without bringing resistive load to the output stage or unwanted effects to the input stage. The frequency compensation of the EA is also reused in the voltage limiting loop to make the whole block more compact. The circuit is implemented in a $0.35~\mu \text{m}$ BCD process. The verification results match the theoretical analysis very well, which proves that the proposed voltage clamper can effectively enhance transient response of the converter control loop and improve system reliability. Only additional 0.001689 mm2 active area is occupied for about 2X transient speed improvement with fair open loop amplifying performance.

  • ISCAS - A Capacitor-less LDO With Fast-transient Error Amplifier and Push-pull Differentiator
    2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018
    Co-Authors: Xin Ming, Shaowei Zhen, Zhang Jiahao, Zhang Chunqi, Qin Yao, Bo Zhang
    Abstract:

    This paper presents a fully-integrated and fast-transient capacitor-less low-dropout regulator (LDO) with high loop gain and bandwidth in full load range for SoC application. It utilizes a combination of a signal- and transient-current boosting (STCB) Error Amplifier (EA) with transient enhancement circuit (TEC) and a push-pull differentiator to drive gate capacitance of the power transistor. The STCB-based EA with TEC ensures fast response of the regulator and the differentiator is also adopted to enhance the loop stability while improving transient response simultaneously. Moreover, adaptive biasing is implemented in the circuit to compensate decrease of loop gain and bandwidth at heavy load. The proposed LDO is fabricated in a 0.5μm CMOS process and occupies an active chip area of 0.077mm2. Simulation results demonstrate that it can deliver 100mA load current at 100mV dropout voltage. The voltage spike at the output, undergoing a maximum load current change, is controlled below 300mV and good line/load regulation is achieved at the same time.

  • on chip compensated Error Amplifier for voltage mode buck converters
    International Conference on Communications Circuits and Systems, 2010
    Co-Authors: Shaowei Zhen, Bo Zhang, Ping Luo, Jun Chen
    Abstract:

    An on-chip compensated Error Amplifier in a voltage-mode buck converter is proposed in the paper. The compensated Error Amplifier is composed of two blocks, unit gain zero generation block and gain block, realizing phase shift and gain of the feedback loop, respectively. Compared to conventional type III compensated Error Amplifier in voltage-mode buck converter, the proposed circuit has much smaller passive component values, enabling full integration of the voltage mode buck converter in SoC. The converter is designed in 0.13µm CMOS process, operating typically at 1.5 MHz pulse width modulation (PWM). The simulation results show the converter with on-chip compensated Error Amplifier achieves both 0.3% load regulation and 10µs load step response time for load step between 200mA and 700mA.

Yatto Wong - One of the best experts on this subject based on the ideXlab platform.

  • near threshold startup integrated boost converter with slew rate enhanced Error Amplifier
    International Symposium on Circuits and Systems, 2009
    Co-Authors: Yatto Wong, Homing Wan, Kwokkuen Kwong, Yathei Lam
    Abstract:

    An integrated voltage-mode boost converter that starts up at 0.9V is successfully implemented in a standard 3.3/5V 0.6µm CMOS process with V tn =0.7V and |V tp |=0.8V. The special features are: (1) a near-threshold soft-start circuit that keeps maximum in-rush current under control; (2) a slew rate enhanced Error Amplifier that achieves stable response over a wide range of supply voltage; and (3) a capacitor multiplier in implementing the compensation capacitor that reduces die area. Maximum efficiency of 93% is achieved at an output power of 260mW.

  • ISCAS - Near-threshold startup integrated boost converter with slew rate enhanced Error Amplifier
    2009 IEEE International Symposium on Circuits and Systems, 2009
    Co-Authors: Yatto Wong, Homing Wan, Kwokkuen Kwong, Yathei Lam
    Abstract:

    An integrated voltage-mode boost converter that starts up at 0.9V is successfully implemented in a standard 3.3/5V 0.6µm CMOS process with V tn =0.7V and |V tp |=0.8V. The special features are: (1) a near-threshold soft-start circuit that keeps maximum in-rush current under control; (2) a slew rate enhanced Error Amplifier that achieves stable response over a wide range of supply voltage; and (3) a capacitor multiplier in implementing the compensation capacitor that reduces die area. Maximum efficiency of 93% is achieved at an output power of 260mW.