The Experts below are selected from a list of 28692 Experts worldwide ranked by ideXlab platform
Francis G. Wolff - One of the best experts on this subject based on the ideXlab platform.
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interactive presentation a new asymmetric sram cell to reduce soft Errors and leakage power in fpga
Design Automation and Test in Europe, 2007Co-Authors: B. S. Gill, Christos A. Papachristou, Francis G. WolffAbstract:Soft Errors in semiconductor memories occur due to charged particle strikes at the cell nodes. In this paper, we present a new asymmetric memory cell to increase the soft Error Tolerance of SRAM. At the same time, this cell can be used at the reduced supply voltage to decrease the leakage power without significantly increasing the soft Error rate of SRAM. A major use of this cell is in the configuration memory of FPGA. The cell is designed using a 70nm process technology and verified using Spice simulations. Soft Error Tolerance results are presented and compared with standard SRAM cell and an existing increased soft Error Tolerance cell. Simulation results show that our cell has lowest soft Error rate at the various supply voltages.
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A New Asymmetric SRAM Cell to Reduce Soft Errors and Leakage Power in FPGA
2007 Design Automation & Test in Europe Conference & Exhibition, 2007Co-Authors: B. S. Gill, Christos A. Papachristou, Francis G. WolffAbstract:Soft Errors in semiconductor memories occur due to charged particle strikes at the cell nodes. In this paper, we present a new asymmetric memory cell to increase the soft Error Tolerance of SRAM. At the same time, this cell can be used at the reduced supply voltage to decrease the leakage power without significantly increasing the soft Error rate of SRAM. A major use of this cell is in the configuration memory of FPGA. The cell is designed using a 70nm process technology and verified using Spice simulations. Soft Error Tolerance results are presented and compared with standard SRAM cell and an existing increased soft Error Tolerance cell. Simulation results show that our cell has lowest soft Error rate at the various supply voltages
Rakesh Kumar - One of the best experts on this subject based on the ideXlab platform.
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Branch and data herding: Reducing control and memory divergence for Error-tolerant GPU applications
2014Co-Authors: John Sartori, Rakesh KumarAbstract:Abstract—Control and memory divergence between threads within the same execution bundle, or warp, have been shown to cause significant performance bottlenecks for GPU applications. In this paper, we exploit the observation that many GPU applications exhibit Error Tolerance to propose branch and data herding. Branch herding eliminates control divergence by forcing all threads in a warp to take the same control path. Data herding eliminates memory divergence by forcing each thread in a warp to load from the same memory block. To safely and efficiently support branch and data herding, we propose a static analysis and compiler framework to prevent exceptions when control and data Errors are introduced, a profiling framework that aims to maximize performance while maintaining acceptable output quality, and hardware optimizations to improve the performance benefits of exploiting Error Tolerance through branch and data herding. Our software implementation of branch herding on NVIDIA GeForce GTX 480 improves performance by up to 34 % (13%, on average) for a suite of NVIDIA CUDA SDK and Parboil [16] benchmarks. Our hardware implementation of branch herding improves performance by up to 55 % (30%, on average). Data herding improves performance by up to 32 % (25%, on average). Observed output quality degradation is minimal for several applications that exhibit Error Tolerance, especially for visual computing applications. EDICS: Parallel Architectures and Design Techniques I
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branch and data herding reducing control and memory divergence for Error tolerant gpu applications
International Conference on Parallel Architectures and Compilation Techniques, 2012Co-Authors: John Sartori, Rakesh KumarAbstract:Control and memory divergence between threads in the same execution bundle, or warp, can significantly throttle the performance of GPU applications. We exploit the observation that many GPU applications exhibit Error Tolerance to propose branch and data herding. Branch herding eliminates control divergence by forcing all threads in a warp to take the same control path. Data herding eliminates memory divergence by forcing each thread in a warp to load from the same memory block. To safely and efficiently support branch and data herding, we propose a static analysis and compiler framework to prevent exceptions when control and data Errors are introduced, a profiling framework that aims to maximize performance while maintaining acceptable output quality, and hardware optimizations to improve the performance benefits of exploiting Error Tolerance through branch and data herding. Our software implementation of branch herding on NVIDIA GeForce GTX 480 improves performance by up to 34% (13%, on average) for a suite of NVIDIA CUDA SDK and Parboil [7] benchmarks. Our hardware implementation of branch herding improves performance by up to 55% (30%, on average). Data herding improves performance by up to 32% (25%, on average). Observed output quality degradation is minimal for several applications that exhibit Error Tolerance, especially for visual computing applications. For a more detailed exposition of this work, see [6].
B. S. Gill - One of the best experts on this subject based on the ideXlab platform.
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interactive presentation a new asymmetric sram cell to reduce soft Errors and leakage power in fpga
Design Automation and Test in Europe, 2007Co-Authors: B. S. Gill, Christos A. Papachristou, Francis G. WolffAbstract:Soft Errors in semiconductor memories occur due to charged particle strikes at the cell nodes. In this paper, we present a new asymmetric memory cell to increase the soft Error Tolerance of SRAM. At the same time, this cell can be used at the reduced supply voltage to decrease the leakage power without significantly increasing the soft Error rate of SRAM. A major use of this cell is in the configuration memory of FPGA. The cell is designed using a 70nm process technology and verified using Spice simulations. Soft Error Tolerance results are presented and compared with standard SRAM cell and an existing increased soft Error Tolerance cell. Simulation results show that our cell has lowest soft Error rate at the various supply voltages.
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A New Asymmetric SRAM Cell to Reduce Soft Errors and Leakage Power in FPGA
2007 Design Automation & Test in Europe Conference & Exhibition, 2007Co-Authors: B. S. Gill, Christos A. Papachristou, Francis G. WolffAbstract:Soft Errors in semiconductor memories occur due to charged particle strikes at the cell nodes. In this paper, we present a new asymmetric memory cell to increase the soft Error Tolerance of SRAM. At the same time, this cell can be used at the reduced supply voltage to decrease the leakage power without significantly increasing the soft Error rate of SRAM. A major use of this cell is in the configuration memory of FPGA. The cell is designed using a 70nm process technology and verified using Spice simulations. Soft Error Tolerance results are presented and compared with standard SRAM cell and an existing increased soft Error Tolerance cell. Simulation results show that our cell has lowest soft Error rate at the various supply voltages
M A Breuer - One of the best experts on this subject based on the ideXlab platform.
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ones counting based Error rate estimation for multiple output circuits
2008 IEEE International Workshop on Design and Test of Nano Devices Circuits and Systems, 2008Co-Authors: Zhaoliang Pan, M A BreuerAbstract:As feature size reduces to nanoscale, it becomes increasingly more expensive and difficult to reach a desired level of yield. Error-Tolerance, which advocates the use of defective chips in systems as long as acceptable performance is obtained, has been proposed as a new way to enhance effective yield. As distinct from classical test, test for Error-Tolerance focuses on quantifying the Error-metrics for acceptability of defective chips. Error-rate is one such metric. To estimate Error-rate, a signature analysis based method and a ones counting based method have been previously proposed. Unfortunately, the ones counting based Error-rate estimation method previously reported must be applied to each output of a multioutput circuit one line at a time. In this paper, we present a method for applying this ones counting technique to a multioutput circuit, i.e., to a pattern rather than a bit. We divide this problem into four parts and present the solution to three or them; the fourth is still an open problem.
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an Error rate based test methodology to support Error Tolerance
IEEE Transactions on Reliability, 2008Co-Authors: Tong-yu Hsieh, Kuen-jong Lee, M A BreuerAbstract:Error-Tolerance is an innovative technique to address the problem of low yields in nanometer very large scale integrated (VLSI) circuitry, which is the backbone of the system-on-a-chip (SOC) revolution. The basic principle of Error-Tolerance is that some chips may occasionally produce erroneous outputs, but still provide acceptable performance when used in certain systems. Using these chips in such systems results in an increase in effective yield. In this paper, a fault-oriented test methodology is presented for classifying whether or not a chip is acceptable based on Error rate estimation. A sampling method is proposed to estimate Error rate associated with each possible fault in the target circuit. According to this information, an approach is developed to identify a list of faults that are acceptable with respect to a specified upper bound on expected Error rates of acceptable chips. Furthermore, a test pattern selection method, and an output masking technique are presented to identify tests which detect all of the unacceptable faults, and as few acceptable faults as possible, so as to maximize the effective yield. Experimental results indicate the high effectiveness of the proposed Error rate estimation method, and the degree to which yield can be enhanced.
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an illustrated methodology for analysis of Error Tolerance
IEEE Design & Test of Computers, 2008Co-Authors: M A Breuer, Haiyang ZhuAbstract:Noise, defects, and process variations are likely to cause very unpredictable circuit performance in future billion-transistor dies, hence decreasing raw yield. Error Tolerance is one of several techniques that can increase effective yield. This article presents a methodology for analyzing the suitability of Error Tolerance for a particular application and implementation. The methodology, illustrated here by a digital telephone-answering device, is applicable to a broad class of systems.
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reduction of detected acceptable faults for yield improvement via Error Tolerance
Design Automation and Test in Europe, 2007Co-Authors: Tong-yu Hsieh, Kuen-jong Lee, M A BreuerAbstract:Error-Tolerance is an innovative way to enhance the effective yield of IC products. Previously a test methodology based on Error-rate estimation to support Error-Tolerance was proposed. Without violating the system Error-rate constraint specified by the user, this methodology identifies a set of faults that can be ignored during testing, thereby leading to a significant improvement in yield. However, usually the patterns detecting all of the unacceptable faults also detect a large number of acceptable faults, resulting in a degradation in achievable yield improvement. In this paper, the authors first provide a probabilistic analysis of this problem and show that a conventional ATPG procedure cannot adequately address this problem. The authors then present a novel test pattern selection procedure and an output masking technique to deal with this problem. The selection process generates a test set aimed to detect all unacceptable faults but as few acceptable faults as possible. The masking technique then examines the generated test patterns and identifies a list of output lines that can be masked (not observed) during testing so as to further avoid the detection of acceptable faults. Experimental results show that by employing the proposed techniques, only a small number of acceptable faults are still detected. In many cases the actual yield improvement approaches the optimal value that can be achieved
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Error Tolerance and multi media
Information Hiding, 2006Co-Authors: M A Breuer, Haiyang ZhuAbstract:Error-Tolerance deals with the use of defective circuitry that occasionally produces Errors, yet provides acceptable performance to end users when executing certain applications. The motivation for using such devices is the related increase in effective yield, and hence lower cost parts. We present a framework for the analysis of the applicability of Error-Tolerance. The framework is illustrated with respect to a digital telephone-answering device, but is applicable to a broad class of multi-media systems. Key components of this framework are: defining acceptable yet imperfect behavior; determining if a large class of realistic defects in a subsystem provide acceptable behavior at the system level; and determining how to recognize (test) if a defective subsystem will provide acceptable system performance.
Yuichiro Fujiwara - One of the best experts on this subject based on the ideXlab platform.
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Self-Synchronizing Pulse Position Modulation with Error Tolerance
2016Co-Authors: Yuichiro FujiwaraAbstract:Abstract—Pulse position modulation (PPM) is a popular signal modulation technique which converts signals into M-ary data by means of the position of a pulse within a time interval. While PPM and its variations have great advantages in many contexts, this type of modulation is vulnerable to loss of synchronization, potentially causing a severe Error floor or throughput penalty even when little or no noise is assumed. Another disadvantage is that this type of modulation typically offers no Error correction mechanism on its own, making them sensitive to intersymbol interference and environmental noise. In this paper we propose a coding theoretic variation of PPM that allows for significantly more efficient symbol and frame synchronization as well as strong Error correction. The proposed scheme can be divided into a synchronization layer and a modulation layer. This makes our technique compatible with major existing techniques such as standard PPM, multipulse PPM, and expurgated PPM as well in that the scheme can be realized by adding a simple synchronization layer to one of these standard techniques. We also develop a generalization of expurgated PPM suited for the modulation layer of the proposed self-synchronizing modulation scheme. This generalized PPM can also be used as stand-alone Error-correcting PPM with a larger number of available symbols. Index Terms—Pulse position modulation, PPM, synchroniza-tion, Error correction, self-synchronizing code, comma-free code, combinatorial design, optical orthogonal code. I
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Self-Synchronizing Pulse Position Modulation With Error Tolerance
IEEE Transactions on Information Theory, 2013Co-Authors: Yuichiro FujiwaraAbstract:Pulse position modulation (PPM) is a popular signal modulation technique which converts signals into M-ary data by means of the position of a pulse within a time interval. While PPM and its variations have great advantages in many contexts, this type of modulation is vulnerable to loss of synchronization, potentially causing a severe Error floor or throughput penalty even when little or no noise is assumed. Another disadvantage is that this type of modulation typically offers no Error correction mechanism on its own, making them sensitive to intersymbol interference and environmental noise. In this paper, we propose a coding theoretic variation of PPM that allows for significantly more efficient symbol and frame synchronization as well as strong Error correction. The proposed scheme can be divided into a synchronization layer and a modulation layer. This makes our technique compatible with major existing techniques such as standard PPM, multipulse PPM, and expurgated PPM as well in that the scheme can be realized by adding a simple synchronization layer to one of these standard techniques. We also develop a generalization of expurgated PPM suited for the modulation layer of the proposed self-synchronizing modulation scheme. This generalized PPM can also be used as stand-alone Error-correcting PPM with a larger number of available symbols.
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self synchronizing pulse position modulation with Error Tolerance
arXiv: Information Theory, 2013Co-Authors: Yuichiro FujiwaraAbstract:Pulse position modulation (PPM) is a popular signal modulation technique which creates M-ary data by means of the position of a pulse within a time interval. While PPM and its variations have great advantages in many contexts, this type of modulation is vulnerable to loss of synchronization, potentially causing a severe Error floor or throughput penalty even when little or no noise is assumed. Another disadvantage is that this type of modulation typically offers no Error correction mechanism on its own, making them sensitive to intersymbol interference and environmental noise. In this paper we propose a coding theoretic variation of PPM that allows for significantly more efficient symbol and frame synchronization as well as strong Error correction. The proposed scheme can be divided into a synchronization layer and a modulation layer. This makes our technique compatible with major existing techniques such as standard PPM, multipluse PPM, and expurgated PPM as well in that the scheme can be realized by adding a simple synchronization layer to one of these standard techniques. We also develop a generalization of expurgated PPM suited for the modulation layer of the proposed self-synchronizing modulation scheme. This generalized PPM can also be used as stand-alone Error-correcting PPM with a larger number of available symbols.
