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Sushil K Prasad - One of the best experts on this subject based on the ideXlab platform.
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parallelizing a sequential logic simulator using an optimistic framework based on a global parallel heap event queue an experience and performance report
Workshop on Parallel and Distributed Simulation, 2000Co-Authors: Sushil K Prasad, Nikhil JunankarAbstract:We have parallelized the Iowa Logic Simulator, a gate-level fine-grained discrete-event simulator, by employing an optimistic algorithm framework based on a global event queue implemented as a parallel heap. The original code and the basic data structures of the serial simulator remained unchanged. Wrapper data structures for the logical processes (gates) and the events are created to allow rollbacks, all the earliest events at each logical processes are stored into the parallel heap, and multiple earliest events are simulated repeatedly by invoking the simulate function of the serial simulator. The parallel heap allowed extraction of hundreds to thousands of earliest events in each queue access. On a bus-based shared-memory multiprocessor, simulation of synthetic circuits with 250,000 gates yielding speedups of 3.3 employing five processors compared to the serial execution time of the Iowa Logic Simulator, and limited the number of rollbacks to within 2,000. The basic steps of parallelization are well-defined and general enough to be employable on other discrete-event simulators.
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PADS - Effectiveness of global event queues in rollback reduction and load balancing
1995Co-Authors: Sushil K Prasad, Basem NaqibAbstract:Compared to highly optimized optimistic simulators which use local event queues for individual processors on a shared-memory computer, we demonstrate that employing a single global event queue drastically reduces the number of rollbacks, brings down the storage requirements, and achieves superior load balance. On a bus-based Silicon Graphics multiprocessor, these virtues consistently translated into faster execution times and higher speedups on those synthetic networks of medium- to coarse-grained logical processes which were ridden with rollbacks and load imbalance on local-queue-based simulators. A dynamic randomization-based load distribution scheme for local-Event-Queue simulators is also shown to be an effective improvement.
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Effectiveness of global event queues in rollback reduction and load balancing
ACM SIGSIM Simulation Digest, 1995Co-Authors: Sushil K Prasad, Basem NaqibAbstract:Compared to highly optimized optimistic simulators which use local event queues for individual processors on a shared-memory computer, we demonstrate that employing a single global event queue drastically reduces the number of rollbacks, brings down the storage requirements, and achieves superior load balance. On a bus-based Silicon Graphics multiprocessor, these virtues consistently translated into faster execution times and higher speedups on those synthetic networks of medium- to coarse-grained logical processes which were ridden with rollbacks and load imbalance on local-queue-based simulators. A dynamic randomization-based load distribution scheme for local-Event-Queue simulators is also shown to be an effective improvement.
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PADS - Parallelizing a sequential logic simulator using an optimistic framework based on a global parallel heap event queue: an experience and performance report
Proceedings Fourteenth Workshop on Parallel and Distributed Simulation, 1Co-Authors: Sushil K Prasad, Nikhil JunankarAbstract:We have parallelized the Iowa Logic Simulator, a gate-level fine-grained discrete-event simulator, by employing an optimistic algorithm framework based on a global event queue implemented as a parallel heap. The original code and the basic data structures of the serial simulator remained unchanged. Wrapper data structures for the logical processes (gates) and the events are created to allow rollbacks, all the earliest events at each logical processes are stored into the parallel heap, and multiple earliest events are simulated repeatedly by invoking the simulate function of the serial simulator. The parallel heap allowed extraction of hundreds to thousands of earliest events in each queue access. On a bus-based shared-memory multiprocessor, simulation of synthetic circuits with 250,000 gates yielding speedups of 3.3 employing five processors compared to the serial execution time of the Iowa Logic Simulator, and limited the number of rollbacks to within 2,000. The basic steps of parallelization are well-defined and general enough to be employable on other discrete-event simulators.
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Using parallel data structures in optimistic discrete event simulation of varying granularity on shared-memory computers
Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing, 1Co-Authors: Sushil K Prasad, S.i. Sawant, B. NaqibAbstract:We investigate a variety of parallel priority queue data structures to implement the global event queue of the optimistic discrete event simulation. The choice of the data structure is shown to depend on the granularity of the events. For medium-to-coarse-grained systems, a moderately fast data structure, such as a parallelized calendar queue, suffices. For fine-grained systems, such as the logic circuits, a sophisticated data structure, namely, parallel heap, was found necessary to exploit the underlying concurrency. With a suitable choice of data structure, we experimentally demonstrate speedups from two to four using six processors of a small bus-based shared-memory computer. Such speedups are possible because our simulators are based on global event queues which resulted in a drastically reduced rollback frequency and an excellent dynamic load balance, two main problems associated with local-Event-Queue-based optimistic simulators. In these experiments, the coarse-and the medium-grained networks were carefully selected to cause numerous rollbacks and severe load imbalance in local-Event-Queue-based simulators. For fine-gained networks, even the global-queue-based simulators which do not employ parallel heap could not achieve any speedup. We include performance data on three simulators based on parallelized calendar queues and a logic simulator based on parallel heaps. >
Nikhil Junankar - One of the best experts on this subject based on the ideXlab platform.
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parallelizing a sequential logic simulator using an optimistic framework based on a global parallel heap event queue an experience and performance report
Workshop on Parallel and Distributed Simulation, 2000Co-Authors: Sushil K Prasad, Nikhil JunankarAbstract:We have parallelized the Iowa Logic Simulator, a gate-level fine-grained discrete-event simulator, by employing an optimistic algorithm framework based on a global event queue implemented as a parallel heap. The original code and the basic data structures of the serial simulator remained unchanged. Wrapper data structures for the logical processes (gates) and the events are created to allow rollbacks, all the earliest events at each logical processes are stored into the parallel heap, and multiple earliest events are simulated repeatedly by invoking the simulate function of the serial simulator. The parallel heap allowed extraction of hundreds to thousands of earliest events in each queue access. On a bus-based shared-memory multiprocessor, simulation of synthetic circuits with 250,000 gates yielding speedups of 3.3 employing five processors compared to the serial execution time of the Iowa Logic Simulator, and limited the number of rollbacks to within 2,000. The basic steps of parallelization are well-defined and general enough to be employable on other discrete-event simulators.
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PADS - Parallelizing a sequential logic simulator using an optimistic framework based on a global parallel heap event queue: an experience and performance report
Proceedings Fourteenth Workshop on Parallel and Distributed Simulation, 1Co-Authors: Sushil K Prasad, Nikhil JunankarAbstract:We have parallelized the Iowa Logic Simulator, a gate-level fine-grained discrete-event simulator, by employing an optimistic algorithm framework based on a global event queue implemented as a parallel heap. The original code and the basic data structures of the serial simulator remained unchanged. Wrapper data structures for the logical processes (gates) and the events are created to allow rollbacks, all the earliest events at each logical processes are stored into the parallel heap, and multiple earliest events are simulated repeatedly by invoking the simulate function of the serial simulator. The parallel heap allowed extraction of hundreds to thousands of earliest events in each queue access. On a bus-based shared-memory multiprocessor, simulation of synthetic circuits with 250,000 gates yielding speedups of 3.3 employing five processors compared to the serial execution time of the Iowa Logic Simulator, and limited the number of rollbacks to within 2,000. The basic steps of parallelization are well-defined and general enough to be employable on other discrete-event simulators.
Satish Narayanasamy - One of the best experts on this subject based on the ideXlab platform.
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ISCA - Accelerating asynchronous programs through event sneak peek
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015Co-Authors: Gaurav Chadha, Scott Mahlke, Satish NarayanasamyAbstract:Asynchronous or event-driven programming is now being used to develop a wide range of systems, including mobile and Web 2.0 applications, Internet-of-Things, and even distributed servers. We observe that these programs perform poorly on conventional processor architectures that are heavily optimized for the characteristics of synchronous programs. Execution characteristics of asynchronous programs significantly differ from synchronous programs as they interleave short events from varied tasks in a fine-grained manner. This paper proposes the Event Sneak Peek (ESP) architecture to mitigate microarchitectural bottlenecks in asynchronous programs. ESP exploits the fact that events are posted to an event queue before they get executed. By exposing this event queue to the processor, ESP gains knowledge of the future events. Instead of stalling on long latency cache misses, ESP jumps ahead to pre-execute future events and gathers useful information that later help initiate accurate instruction and data prefetches and correct branch mispredictions. We demonstrate that ESP improves the performance of popular asynchronous Web 2.0 applications including Amazon, Google maps, and Facebook, by an average of 16%.
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Accelerating asynchronous programs through event sneak peek
ACM SIGARCH Computer Architecture News, 2015Co-Authors: Gaurav Chadha, Scott Mahlke, Satish NarayanasamyAbstract:Asynchronous or event-driven programming is now being used to develop a wide range of systems, including mobile and Web 2.0 applications, Internet-of-Things, and even distributed servers. We observe that these programs perform poorly on conventional processor architectures that are heavily optimized for the characteristics of synchronous programs. Execution characteristics of asynchronous programs significantly differ from synchronous programs as they interleave short events from varied tasks in a fine-grained manner. This paper proposes the Event Sneak Peek (ESP) architecture to mitigate microarchitectural bottlenecks in asynchronous programs. ESP exploits the fact that events are posted to an event queue before they get executed. By exposing this event queue to the processor, ESP gains knowledge of the future events. Instead of stalling on long latency cache misses, ESP jumps ahead to pre-execute future events and gathers useful information that later help initiate accurate instruction and data prefetches and correct branch mispredictions. We demonstrate that ESP improves the performance of popular asynchronous Web 2.0 applications including Amazon, Google maps, and Facebook, by an average of 16%.
Rupak Majumdar - One of the best experts on this subject based on the ideXlab platform.
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TACAS - Partial Order Reduction for Event-Driven Multi-threaded Programs
Tools and Algorithms for the Construction and Analysis of Systems, 2016Co-Authors: Pallavi Maiya, Rahul Gupta, Aditya Kanade, Rupak MajumdarAbstract:Event-driven multi-threaded programming is fast becoming a preferred style of developing efficient and responsive applications. In this concurrency model, multiple threads execute concurrently, communicating through shared objects as well as by posting asynchronous events. In this work, we consider partial order reduction POR for this concurrency model. Existing POR techniques treat event queues associated with threads as shared objects and reorder every pair of events handled on the same thread even if reordering them does not lead to different states. We do not treat event queues as shared objects and propose a new POR technique based on a backtracking set called the dependence-covering set. Our POR technique reorders events handled by the same thread only if necessary. We prove that exploring dependence-covering sets suffices to detect all deadlock cycles and assertion violations defined over local variables. To evaluate effectiveness of our POR scheme, we have implemented a dynamic algorithm to compute dependence-covering sets. On execution traces of some Android applications, we demonstrate that our technique explores many fewer transitions --often orders of magnitude fewer-- compared to exploration based on persistent sets, in which event queues are considered as shared objects.
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A Partial Order Reduction Technique for Event-driven Multi-threaded Programs
arXiv: Programming Languages, 2015Co-Authors: Pallavi Maiya, Rahul Gupta, Aditya Kanade, Rupak MajumdarAbstract:Event-driven multi-threaded programming is fast becoming a preferred style of developing efficient and responsive applications. In this concurrency model, multiple threads execute concurrently, communicating through shared objects as well as by posting asynchronous events that are executed in their order of arrival. In this work, we consider partial order reduction (POR) for event-driven multi-threaded programs. The existing POR techniques treat event queues associated with threads as shared objects and thereby, reorder every pair of events handled on the same thread even if reordering them does not lead to different states. We do not treat event queues as shared objects and propose a new POR technique based on a novel backtracking set called the dependence-covering set. Events handled by the same thread are reordered by our POR technique only if necessary. We prove that exploring dependence-covering sets suffices to detect all deadlock cycles and assertion violations defined over local variables. To evaluate effectiveness of our POR scheme, we have implemented a dynamic algorithm to compute dependence-covering sets. On execution traces obtained from a few Android applications, we demonstrate that our technique explores many fewer transitions ---often orders of magnitude fewer--- compared to exploration based on persistent sets, wherein, event queues are considered as shared objects.
Gaurav Chadha - One of the best experts on this subject based on the ideXlab platform.
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ISCA - Accelerating asynchronous programs through event sneak peek
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015Co-Authors: Gaurav Chadha, Scott Mahlke, Satish NarayanasamyAbstract:Asynchronous or event-driven programming is now being used to develop a wide range of systems, including mobile and Web 2.0 applications, Internet-of-Things, and even distributed servers. We observe that these programs perform poorly on conventional processor architectures that are heavily optimized for the characteristics of synchronous programs. Execution characteristics of asynchronous programs significantly differ from synchronous programs as they interleave short events from varied tasks in a fine-grained manner. This paper proposes the Event Sneak Peek (ESP) architecture to mitigate microarchitectural bottlenecks in asynchronous programs. ESP exploits the fact that events are posted to an event queue before they get executed. By exposing this event queue to the processor, ESP gains knowledge of the future events. Instead of stalling on long latency cache misses, ESP jumps ahead to pre-execute future events and gathers useful information that later help initiate accurate instruction and data prefetches and correct branch mispredictions. We demonstrate that ESP improves the performance of popular asynchronous Web 2.0 applications including Amazon, Google maps, and Facebook, by an average of 16%.
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Accelerating asynchronous programs through event sneak peek
ACM SIGARCH Computer Architecture News, 2015Co-Authors: Gaurav Chadha, Scott Mahlke, Satish NarayanasamyAbstract:Asynchronous or event-driven programming is now being used to develop a wide range of systems, including mobile and Web 2.0 applications, Internet-of-Things, and even distributed servers. We observe that these programs perform poorly on conventional processor architectures that are heavily optimized for the characteristics of synchronous programs. Execution characteristics of asynchronous programs significantly differ from synchronous programs as they interleave short events from varied tasks in a fine-grained manner. This paper proposes the Event Sneak Peek (ESP) architecture to mitigate microarchitectural bottlenecks in asynchronous programs. ESP exploits the fact that events are posted to an event queue before they get executed. By exposing this event queue to the processor, ESP gains knowledge of the future events. Instead of stalling on long latency cache misses, ESP jumps ahead to pre-execute future events and gathers useful information that later help initiate accurate instruction and data prefetches and correct branch mispredictions. We demonstrate that ESP improves the performance of popular asynchronous Web 2.0 applications including Amazon, Google maps, and Facebook, by an average of 16%.