The Experts below are selected from a list of 291303 Experts worldwide ranked by ideXlab platform
David A Wood - One of the best experts on this subject based on the ideXlab platform.
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Fine Grain task aggregation and coordination on gpus
International Symposium on Computer Architecture, 2014Co-Authors: Marc S Orr, Bradford M Beckmann, Steven K Reinhardt, David A WoodAbstract:In general-purpose graphics processing unit (GPGPU) computing, data is processed by concurrent threads execut-ing the same function. This model, dubbed single-instruction/multiple-thread (SIMT), requires programmers to coordinate the synchronous execution of similar opera-tions across thousands of data elements. To alleviate this programmer burden, Gaster and Howes outlined the chan-nel abstraction, which facilitates dynamically aggregating asynchronously produced Fine-Grain work into coarser-Grain tasks. However, no practical implementation has been proposed To this end, we propose and evaluate the first channel im-plementation. To demonstrate the utility of channels, we present a case study that maps the Fine-Grain, recursive task spawning in the Cilk programming language to channels by representing it as a flow graph. To support data-parallel recursion in bounded memory, we propose a hardware mechanism that allows wavefronts to yield their execution resources. Through channels and wavefront yield, we im-plement four Cilk benchmarks. We show that Cilk can scale with the GPU architecture, achieving speedups of as much as 4.3x on eight compute units
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HPCA - Parallel Dispatch Queue: a queue-based programming abstraction to parallelize Fine-Grain communication protocols
Proceedings Fifth International Symposium on High-Performance Computer Architecture, 1999Co-Authors: Babak Falsafi, David A WoodAbstract:This paper proposes a novel queue-based programming abstraction, Parallel Dispatch Queue (PDQ), that enables efficient parallel execution of Fine-Grain software communication protocols. Parallel systems often use Fine-Grain software handlers to integrate a network message into computation. Executing such handlers in parallel requires access synchronization around resources. Much as a monitor construct in a concurrent language protects accesses to a set of data structures, PDQ allows messages to include a synchronization key protecting handler accesses to a group of protocol resources. By simply synchronizing messages in a queue prior to dispatch, PDQ not only eliminates the overhead of acquiring/releasing synchronization primitives but also prevents busy-waiting within handlers. In this paper, we study PDQ's impact on software protocol performance in the context of Fine-Grain distributed shared memory (DSM) on an SMP cluster. Simulation results running shared-memory applications indicate that: (i) parallel software protocol execution using PDQ significantly improves performance in Fine-Grain DSM, (ii) tight integration of PDQ and embedded processors into a single custom device can offer performance competitive or better than an all-hardware DSM, and (iii) PDQ best benefits cost-effective systems that use idle SMP processors (rather than custom embedded processors) to execute protocols. On a cluster of 4 16-way SMPs, a PDQ-based parallel protocol running on idle SMP processors improves application performance by a factor of 2.6 over a system running a serial protocol on a single dedicated processor.
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Fine Grain access control for distributed shared memory
Architectural Support for Programming Languages and Operating Systems, 1994Co-Authors: Ioannis T. Schoinas, Steven K Reinhardt, Babak Falsafi, Alvin R Lebeck, James R Larus, David A WoodAbstract:This paper discusses implementations of Fine-Grain memory access control, which selectively restricts reads and writes to cache-block-sized memory regions. Fine-Grain access control forms the basis of efficient cache-coherent shared memory. This paper focuses on low-cost implementations that require little or no additional hardware. These techniques permit efficient implementation of shared memory on a wide range of parallel systems, thereby providing shared-memory codes with a portability previously limited to message passing. This paper categorizes techniques based on where access control is enforced and where access conflicts are handled. We incorporated three techniques that require no additional hardware into Blizzard, a system that supports distributed shared memory on the CM-5. The first adds a software lookup before each shared-memory reference by modifying the program's executable. The second uses the memory's error correcting code (ECC) as cache-block valid bits. The third is a hybrid. The software technique ranged from slightly faster to two times slower than the ECC approach. Blizzard's performance is roughly comparable to a hardware shared-memory machine. These results argue that clusters of workstations or personal computers with networks comparable to the CM-5's will be able to support the same shared-memory interfaces as supercomputers.
Tian Zhiling - One of the best experts on this subject based on the ideXlab platform.
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Study on the flash butt welding of 400 MPa ultra-Fine Grain steel
Journal of Materials Engineering and Performance, 2003Co-Authors: Wang Weibin, Shi Yaowu, Sha Peng, Lei Yongping, Tian ZhilingAbstract:A 400 MPa ultra-Fine Grain steel possesses high strength and toughness. Due to its Fine Grain size, the heat affect zone (HAZ) of the weld joint will soften during welding. The weldability of 400 MPa ultra-Fine reinforced steel bar of flash butt welding is investigated by using the micro metallographical examination and macro-mechanical-property tests. The joint of flash butt welding has a superior mechanical property. The HAZ in the weld joint does not show apparent softening. There is only a localized softening spot inside the weld seam, which does not affect the property of the whole joint. Therefore, flash butt welding is appropriate for joining the 400 MPa ultra-Fine Grain reinforced steel bars. The resulting weld joint has excellent mechanical properties.
Xiaoyan Li - One of the best experts on this subject based on the ideXlab platform.
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haz microstructure simulation in welding of a ultra Fine Grain steel
Computational Materials Science, 2004Co-Authors: Dong Chen, Xiaoyan LiAbstract:In the present work the evolution of Grain structure in the weld HAZ (heat affected zone) under welding thermal cycle was simulated. Especially the Grain growth in the HAZ of a SS400 ultra Fine Grain steel was investigated. An integrated 3-D Monte Carlo (MC) simulation system for Grain growth of the weld HAZ was developed based on Microsoft Windows. The results indicate that MC simulation is an effective way to investigate the Grain growth in weld HAZ. The method not only simulates the non-isothermal dynamics process of the Grain growth in the weld HAZ, but also visualizes the austenite Grains realistically. Moreover, the thermal pinning effect can be easily included in the simulation process. The Grain sizes of the CGHAZ (coarse Grain heat affected zone) obtained from MC simulation are basically in agreement with the experimental measurement of the real welded joints under different heat input. Furthermore, the simulation indicates that the Grain growth degree is higher for the SS400 ultra Fine Grain steel compared to conventional steel. With the increase in the heat input, the Grain growth of the CGHAZ rapidly increases. Because the activation energy of the Grain growth is lower for the SS400 ultra Fine Grain steel, austenite Grains can grow at a relatively lower temperature, hence the range of the CGHAZ becomes wider.
Christopher Batten - One of the best experts on this subject based on the ideXlab platform.
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enabling realistic Fine Grain voltage scaling with reconfigurable power distribution networks
International Symposium on Microarchitecture, 2014Co-Authors: Waclaw Godycki, Christopher Torng, Ivan Bukreyev, Alyssa B Apsel, Christopher BattenAbstract:Recent work has shown that monolithic integration of voltage regulators will be feasible in the near future, enabling reduced system cost and the potential for Fine-Grain voltage scaling (FGVS). More specifically, on-chip switched-capacitor regulators appear to offer an attractive trade-off in terms of integration complexity, power density, power efficiency, and response time. In this paper, we use architecture-level modeling to explore a new dynamic voltage/frequency scaling controller called the Fine-Grain synchronization controller (FG-SYNC+). FG-SYNC+ enables improved performance and energy efficiency at similar average power for multithreaded applications with activity imbalance. We then use circuit-level modeling to explore various approaches to organizing on-chip voltage regulation, including a new approach called reconfigurable power distribution networks (RPDNs). RPDNs allow one regulator to "borrow" energy storage from regulators associated with underutilized cores resulting in improved area/power efficiency and faster response times. We evaluate FG-SYNC+ and RPDN using a vertically integrated research methodology, and our results demonstrate a 10 -- 50% performance and 10 -- 70% energy-efficiency improvement on the majority of the applications studied compared to no FGVS, yet RPDN uses 40% less area compared to a more traditional per-core regulation scheme.
Babak Falsafi - One of the best experts on this subject based on the ideXlab platform.
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HPCA - Parallel Dispatch Queue: a queue-based programming abstraction to parallelize Fine-Grain communication protocols
Proceedings Fifth International Symposium on High-Performance Computer Architecture, 1999Co-Authors: Babak Falsafi, David A WoodAbstract:This paper proposes a novel queue-based programming abstraction, Parallel Dispatch Queue (PDQ), that enables efficient parallel execution of Fine-Grain software communication protocols. Parallel systems often use Fine-Grain software handlers to integrate a network message into computation. Executing such handlers in parallel requires access synchronization around resources. Much as a monitor construct in a concurrent language protects accesses to a set of data structures, PDQ allows messages to include a synchronization key protecting handler accesses to a group of protocol resources. By simply synchronizing messages in a queue prior to dispatch, PDQ not only eliminates the overhead of acquiring/releasing synchronization primitives but also prevents busy-waiting within handlers. In this paper, we study PDQ's impact on software protocol performance in the context of Fine-Grain distributed shared memory (DSM) on an SMP cluster. Simulation results running shared-memory applications indicate that: (i) parallel software protocol execution using PDQ significantly improves performance in Fine-Grain DSM, (ii) tight integration of PDQ and embedded processors into a single custom device can offer performance competitive or better than an all-hardware DSM, and (iii) PDQ best benefits cost-effective systems that use idle SMP processors (rather than custom embedded processors) to execute protocols. On a cluster of 4 16-way SMPs, a PDQ-based parallel protocol running on idle SMP processors improves application performance by a factor of 2.6 over a system running a serial protocol on a single dedicated processor.
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Fine Grain access control for distributed shared memory
Architectural Support for Programming Languages and Operating Systems, 1994Co-Authors: Ioannis T. Schoinas, Steven K Reinhardt, Babak Falsafi, Alvin R Lebeck, James R Larus, David A WoodAbstract:This paper discusses implementations of Fine-Grain memory access control, which selectively restricts reads and writes to cache-block-sized memory regions. Fine-Grain access control forms the basis of efficient cache-coherent shared memory. This paper focuses on low-cost implementations that require little or no additional hardware. These techniques permit efficient implementation of shared memory on a wide range of parallel systems, thereby providing shared-memory codes with a portability previously limited to message passing. This paper categorizes techniques based on where access control is enforced and where access conflicts are handled. We incorporated three techniques that require no additional hardware into Blizzard, a system that supports distributed shared memory on the CM-5. The first adds a software lookup before each shared-memory reference by modifying the program's executable. The second uses the memory's error correcting code (ECC) as cache-block valid bits. The third is a hybrid. The software technique ranged from slightly faster to two times slower than the ECC approach. Blizzard's performance is roughly comparable to a hardware shared-memory machine. These results argue that clusters of workstations or personal computers with networks comparable to the CM-5's will be able to support the same shared-memory interfaces as supercomputers.