The Experts below are selected from a list of 1686 Experts worldwide ranked by ideXlab platform

Tong Zhang - One of the best experts on this subject based on the ideXlab platform.

  • over clocked ssd safely running beyond Flash Memory Chip i o clock specs
    High-Performance Computer Architecture, 2014
    Co-Authors: Kai Zhao, Kalyana Sundaram Venkataraman, Xuebin Zhang, Ning Zheng, Tong Zhang
    Abstract:

    This paper presents a design strategy that enables aggressive use of Flash Memory Chip I/O link over-clocking in solid-state drives (SSDs) without sacrificing storage reliability. The gradual wear-out and process variation of NAND Flash Memory makes the worst-case oriented error correction code (ECC) in SSDs largely under-utilized most of the time. This work proposes to opportunistically leverage under-utilized error correction strength to allow error-prone Flash Memory I/O link over-clocking. Its rationale and key design issues are presented and studied in this paper, and its potential effectiveness has been verified through hardware experiments and system simulations. Using sub-22nm NAND Flash Memory Chips with I/O specs of 166MBps, we carried out extensive experiments and show that the proposed design strategy can enable SSDs safely operate with error-prone I/O link running at 275MBps. Trace-driven SSD simulations over a variety of workload traces show the system read response time can be reduced by over 20%.

  • HPCA - Over-clocked SSD: Safely running beyond Flash Memory Chip I/O clock specs
    2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA), 2014
    Co-Authors: Kai Zhao, Kalyana Sundaram Venkataraman, Xuebin Zhang, Ning Zheng, Tong Zhang
    Abstract:

    This paper presents a design strategy that enables aggressive use of Flash Memory Chip I/O link over-clocking in solid-state drives (SSDs) without sacrificing storage reliability. The gradual wear-out and process variation of NAND Flash Memory makes the worst-case oriented error correction code (ECC) in SSDs largely under-utilized most of the time. This work proposes to opportunistically leverage under-utilized error correction strength to allow error-prone Flash Memory I/O link over-clocking. Its rationale and key design issues are presented and studied in this paper, and its potential effectiveness has been verified through hardware experiments and system simulations. Using sub-22nm NAND Flash Memory Chips with I/O specs of 166MBps, we carried out extensive experiments and show that the proposed design strategy can enable SSDs safely operate with error-prone I/O link running at 275MBps. Trace-driven SSD simulations over a variety of workload traces show the system read response time can be reduced by over 20%.

  • Overclocking nand Flash Memory I/O Link in LDPC-Based SSDs
    IEEE Transactions on Circuits and Systems II: Express Briefs, 2014
    Co-Authors: Kai Zhao, Rino Micheloni, Tong Zhang
    Abstract:

    Due to the increasingly significant process variation and gradual Flash Memory cell wear-out, the worst-case-oriented error correction code (ECC) in solid-state drives (SSDs) is mostly underutilized throughout the entire lifetime. Error-prone overclocking of Flash Memory Chip I/O links can trade such ECC underutilization for opportunistically improving SSD speed performance, and its effectiveness strongly depends on how well the ECC decoding can handle the overclocking-induced I/O link errors. As SSDs are quickly adopting low-density parity-check (LDPC) code, this brief concerns LPDC-based overclocked SSDs. Experiments with 20-nm nand Flash Memory Chips reveal unique bit error characteristics of the overclocked I/O link, based upon which this brief develops solutions that can leverage the error characteristics to improve LDPC decoding performance. Results show that the developed techniques can reduce LDPC code decoding power consumption by 60% and reduce the decoding failure rate by over two orders of magnitude.

  • HotStorage - Exploiting heat-accelerated Flash Memory wear-out recovery to enable self-healing SSDs
    2011
    Co-Authors: Guiqiang Dong, Tong Zhang
    Abstract:

    This paper proposes a self-healing solid-state drive (SSD) design strategy that exploits heat-accelerated recovery of NAND Flash Memory cell wear-out to improve SSD lifetime. The key is to make each NAND Flash Memory Chip self-healable by stacking an extra heater die, and to employ system-level redundancy to ensure SSD data storage integrity when one Memory Chip is being self-heated for Memory cell wearout recovery. Based upon detailed thermal modeling and Memory cell device modeling, we carried out simulations and performed detailed analysis. The results show that SSD lifetime can be improved by over five times at reasonable performance and energy consumption overhead.

  • A first study on self-healing solid-state drives
    2011 3rd IEEE International Memory Workshop, IMW 2011, 2011
    Co-Authors: Qi Wu, Guiqiang Dong, Tong Zhang
    Abstract:

    This paper proposes a self-healing solid-state drive (SSD) design strategy that exploits heat-accelerated interface trap recovery of NAND Flash Memory cells to largely improve the SSD lifetime. The key is to make each NAND Flash Memory Chip self-healable by stacking an extra heater die, and employ system-level redundancy to ensure SSD data storage integrity when one NAND Flash Memory Chip is being self-heated for accelerating interface trap recovery. Based upon detailed thermal modeling and Memory cell device modeling, we carried out simulations and analysis, and the results show that this proposed design strategy can potentially improve SSD lifetime by one order of magnitude at reasonable energy consumption overhead.

Lanrong Dung - One of the best experts on this subject based on the ideXlab platform.

  • a nand Flash Memory controller for sd mmc Flash Memory card
    IEEE Transactions on Magnetics, 2007
    Co-Authors: Lanrong Dung
    Abstract:

    In this paper, a novel NAND Flash Memory controller was designed. A t-EC w-bit parallel Bose-Chaudhuri-Hocquengham (BCH) error-correction code (ECC) was designed for correcting the random bit errors of the Flash Memory Chip, which is suitable for the randomly bit errors property and parallel I/O interface of the NAND-type Flash Memory. A code-banking mechanism was designed for the tradeoffs between the controller cost and the in-system programmability (ISP) support. With the ISP functionality and the Flash parameters programmed in the reserved area of the Flash Memory Chip during the card production stage, the function for supporting various kinds of NAND Flash Memory could be provided by a single controller. In addition, built-in defect management and wear-leveling algorithm enhanced the product life cycle and reliability. Dual channel accessing of the Flash Memory provided the good performance in data transfer rate. With respect to the proposed controller architecture, a real secure digital card (SD)/multimedia card (MMC) Flash Memory card controller Chip was designed and implemented with UMC 0.18 mum CMOS process. Experimental results show the designed circuit can fully comply with the system specifications and shows the good performances

  • a nand Flash Memory controller for sd mmc Flash Memory card
    IEEE Transactions on Magnetics, 2007
    Co-Authors: Lanrong Dung
    Abstract:

    In this paper, a novel NAND Flash Memory controller was designed. A t-EC w-bit parallel Bose-Chaudhuri-Hocquengham (BCH) error-correction code (ECC) was designed for correcting the random bit errors of the Flash Memory Chip, which is suitable for the randomly bit errors property and parallel I/O interface of the NAND-type Flash Memory. A code-banking mechanism was designed for the tradeoffs between the controller cost and the in-system programmability (ISP) support. With the ISP functionality and the Flash parameters programmed in the reserved area of the Flash Memory Chip during the card production stage, the function for supporting various kinds of NAND Flash Memory could be provided by a single controller. In addition, built-in defect management and wear-leveling algorithm enhanced the product life cycle and reliability. Dual channel accessing of the Flash Memory provided the good performance in data transfer rate. With respect to the proposed controller architecture, a real secure digital card (SD)/multimedia card (MMC) Flash Memory card controller Chip was designed and implemented with UMC 0.18 mum CMOS process. Experimental results show the designed circuit can fully comply with the system specifications and shows the good performances

  • ICECS - A NAND Flash Memory Controller for SD/MMC Flash Memory Card
    2006 13th IEEE International Conference on Electronics Circuits and Systems, 2006
    Co-Authors: Chuan-sheng Lin, Kuang-yuan Chen, Yu-hsian Wang, Lanrong Dung
    Abstract:

    In this paper, a novel NAND Flash Memory Controller was designed. A t-EC w-bit parallel BCH ECC code was designed for correcting the random bit errors of the Flash Memory Chip, which is suitable for the randomly bit errors property and parallel I/O interface of the NAND type Flash Memory. A Code-Banking mechanism was designed for the trade-offs between the controller cost and the ISP (in system programmability) support. With the ISP functionality and the Flash Parameters programmed in the reserved area of the Flash Memory Chip during the card production stage, the function for supporting various kinds of NAND Flash Memory could be provided by a single controller. In addition, built-in defect management and wear-leveling algorithm enhanced the product life cycle and reliability. Dual Channel accessing of the Flash Memory provided the good performance in data transfer rate. With respect to the proposed controller architecture, a real SD/MMC Flash Memory card controller Chip was designed and implemented with UMC 0.18mum CMOS process. Experimental results show the designed circuit can fully comply with the system specifications and shows the good performances.

Hiroki Ishikuro - One of the best experts on this subject based on the ideXlab platform.

  • 1-W 3.3–16.3-V Boosting Wireless Power Transfer Circuits With Vector Summing Power Controller
    IEEE Journal of Solid-State Circuits, 2012
    Co-Authors: Kazutoshi Tomita, Ryota Shinoda, Tadahiro Kuroda, Hiroki Ishikuro
    Abstract:

    This paper presents SD-card-size wireless power transfer system for large-volume contactless Memory cards. Voltage is boosted simultaneously with power transfer, which eliminates the dc-dc converter or charge-pump circuit for data write operation into the Flash Memory Chip. The proposed approach reduces the number of components and BOM cost and improves the total power efficiency. A vector summing technique is proposed to control the transmitting power and secondary side voltage. The transmitter and rectifier have been designed and fabricated using 0.18-μ m-CMOS with high voltage option. Voltage boost from 3.3 to 16.3 V and 1-W power transfer with 50% total efficiency have been successfully demonstrated, and the response time for the power control loop is shorter than 35 μs .

  • A-SSCC - 1W 3.3V-to-16.3V boosting wireless power transfer circuits with vector summing power controller
    IEEE Asian Solid-State Circuits Conference 2011, 2011
    Co-Authors: Kazutoshi Tomita, Ryota Shinoda, Tadahiro Kuroda, Hiroki Ishikuro
    Abstract:

    This paper presents SD card size wireless power transfer system for large volume contactless Memory cards. Voltage is boosted simultaneously with power transfer, which eliminates the DC-DC converter or charge-pump circuit for data write operation into the Flash Memory Chip. The proposed approach reduces the number of components and BOM cost and improve the total power efficiency. Vector summing technique is proposed to control the transmitting power and secondary side voltage. The transmitter and rectifier have been designed and fabricated using 0.18um-CMOS with high voltage option. Voltage boost from 3.3V to 16.3V and 1W power transfer with 50% total efficiency have been successfully demonstrated.

Kazutoshi Tomita - One of the best experts on this subject based on the ideXlab platform.

  • 1-W 3.3–16.3-V Boosting Wireless Power Transfer Circuits With Vector Summing Power Controller
    IEEE Journal of Solid-State Circuits, 2012
    Co-Authors: Kazutoshi Tomita, Ryota Shinoda, Tadahiro Kuroda, Hiroki Ishikuro
    Abstract:

    This paper presents SD-card-size wireless power transfer system for large-volume contactless Memory cards. Voltage is boosted simultaneously with power transfer, which eliminates the dc-dc converter or charge-pump circuit for data write operation into the Flash Memory Chip. The proposed approach reduces the number of components and BOM cost and improves the total power efficiency. A vector summing technique is proposed to control the transmitting power and secondary side voltage. The transmitter and rectifier have been designed and fabricated using 0.18-μ m-CMOS with high voltage option. Voltage boost from 3.3 to 16.3 V and 1-W power transfer with 50% total efficiency have been successfully demonstrated, and the response time for the power control loop is shorter than 35 μs .

  • A-SSCC - 1W 3.3V-to-16.3V boosting wireless power transfer circuits with vector summing power controller
    IEEE Asian Solid-State Circuits Conference 2011, 2011
    Co-Authors: Kazutoshi Tomita, Ryota Shinoda, Tadahiro Kuroda, Hiroki Ishikuro
    Abstract:

    This paper presents SD card size wireless power transfer system for large volume contactless Memory cards. Voltage is boosted simultaneously with power transfer, which eliminates the DC-DC converter or charge-pump circuit for data write operation into the Flash Memory Chip. The proposed approach reduces the number of components and BOM cost and improve the total power efficiency. Vector summing technique is proposed to control the transmitting power and secondary side voltage. The transmitter and rectifier have been designed and fabricated using 0.18um-CMOS with high voltage option. Voltage boost from 3.3V to 16.3V and 1W power transfer with 50% total efficiency have been successfully demonstrated.

Dandan Li - One of the best experts on this subject based on the ideXlab platform.

  • design of pic microcontroller based high capacity multi channel data acquisition module
    International Conference on Measurement Information and Control, 2012
    Co-Authors: Hongmin Wang, Dandan Li
    Abstract:

    Using MicroChip's PIC microcontroller and the Flash Memory Chip, I designed a high -capacity multi-channel data acquisition module. In the design of the hardware circuit, Focus on the multi-channel data acquisition circuit for PIC16F877 MCU and SPI communication link between the microcontroller and Flash Chip. In software development, Developed A/D conversion process using the PIC16F877 MCU on-Chip A/D converter module in C language, and the entire program of temperature acquisition using the DS18B20. The results show that: Developed a data acquisition module with low cost, simple structure and high reliability features.