The Experts below are selected from a list of 93363 Experts worldwide ranked by ideXlab platform
Yu Chien-cheng - One of the best experts on this subject based on the ideXlab platform.
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Low-Power Double Edge-Triggered Flip-Flop Circuit Design
2008 3rd International Conference on Innovative Computing Information and Control, 2008Co-Authors: Yu Chien-chengAbstract:In this paper, we compare three previously published static double edge-triggered (DET) Flip-Flops with a proposed design for their transistor counts and power consumptions. The proposed DET flip-flop uses only 12 transistors in addition to the clock driver, and hence requires a small area. Several HSPICE simulations with different input sequences show that the proposed DET flip-flop reduces power consumption up to 85%, as compared to conventional DET Flip-Flops.
De Gyvez, José Pineda - One of the best experts on this subject based on the ideXlab platform.
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Low power latch based design with smart retiming
IEEE Computer Society, 2018Co-Authors: Singh Kamlesh, Jiao Hailong, Huisken Jos, Fatemi Hamed, De Gyvez, José PinedaAbstract:Flip-Flops and latches are two options to construct pipelines in digital integrated circuits (ICs). In this paper, the implications for converting a flip-flop based design to a latch-based design are investigated by performing timing and power analysis. Design flows are also proposed to convert a flip-flop based design to a latch-based design as well as a latch/flip-flop-mixed design. With a new retiming strategy, the optimum operating condition is identified for both the latch based design and the mixed design, where the maximum time borrowing or performance enhancement can be obtained. Compared to the flip-flop based design, 48% and 45% frequency boosting are achieved by the latch based design and the mixed design, respectively. While maintaining the same performance as the flip-flop based design with the aid of supply voltage scaling, the latch based design and the mixed design reduce the power consumption by 21% and 16%, respectively, in an industrial 28-nm FDSOI CMOS technology
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Multi-bit pulsed-latch based low power synchronous circuit design
IEEE Computer Society, 2018Co-Authors: Singh Kamlesh, Rosas, Omar Alejandro Rodriguez, Jiao Hailong, Huisken Jos, De Gyvez, José PinedaAbstract:Pulsed-latches emerge as an ideal sequencing element for low power digital circuit design, serving as an alternative of Flip-Flops. In this paper, low power multi-bit pulsed-latches are proposed to construct pipeline stages in synchronous digital circuits. A method of integrating the proposed multi-bit pulsed-latches in the commercial design flows is also introduced. With the multi-bit pulsed-latches, up to 45% power savings are achieved for a variety of ITC benchmark circuits and an ARM Cortex-M0 as compared to the flip-flop based designs in an industrial 28-nm FDSOI CMOS technology. Furthermore, the power consumption of the clock distribution network and the layout area are reduced by up to 83% and 16%, respectively, with the proposed multi-bit pulsed-latches as compared to the flip-flop based designs
Pineda De Gyvez, J José - One of the best experts on this subject based on the ideXlab platform.
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Multi-bit pulsed-latch based low power synchronous circuit design
IEEE Computer Society, 2018Co-Authors: Kk Singh, Oa ,rodriguez Rosas, Jiao H Hailong, Huisken, Ja Jos, Pineda De Gyvez, J JoséAbstract:\u3cp\u3ePulsed-latches emerge as an ideal sequencing element for low power digital circuit design, serving as an alternative of Flip-Flops. In this paper, low power multi-bit pulsed-latches are proposed to construct pipeline stages in synchronous digital circuits. A method of integrating the proposed multi-bit pulsed-latches in the commercial design flows is also introduced. With the multi-bit pulsed-latches, up to 45% power savings are achieved for a variety of ITC benchmark circuits and an ARM Cortex-M0 as compared to the flip-flop based designs in an industrial 28-nm FDSOI CMOS technology. Furthermore, the power consumption of the clock distribution network and the layout area are reduced by up to 83% and 16%, respectively, with the proposed multi-bit pulsed-latches as compared to the flip-flop based designs.\u3c/p\u3
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Low power latch based design with smart retiming
IEEE Computer Society, 2018Co-Authors: Kk Singh, Jiao H Hailong, Huisken, Ja Jos, Fatemi, Sh Hamed, Pineda De Gyvez, J JoséAbstract:\u3cp\u3eFlip-Flops and latches are two options to construct pipelines in digital integrated circuits (ICs). In this paper, the implications for converting a flip-flop based design to a latch-based design are investigated by performing timing and power analysis. Design flows are also proposed to convert a flip-flop based design to a latch-based design as well as a latch/flip-flop-mixed design. With a new retiming strategy, the optimum operating condition is identified for both the latch based design and the mixed design, where the maximum time borrowing or performance enhancement can be obtained. Compared to the flip-flop based design, 48% and 45% frequency boosting are achieved by the latch based design and the mixed design, respectively. While maintaining the same performance as the flip-flop based design with the aid of supply voltage scaling, the latch based design and the mixed design reduce the power consumption by 21% and 16%, respectively, in an industrial 28-nm FDSOI CMOS technology.\u3c/p\u3
Singh Kamlesh - One of the best experts on this subject based on the ideXlab platform.
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Low power latch based design with smart retiming
IEEE Computer Society, 2018Co-Authors: Singh Kamlesh, Jiao Hailong, Huisken Jos, Fatemi Hamed, De Gyvez, José PinedaAbstract:Flip-Flops and latches are two options to construct pipelines in digital integrated circuits (ICs). In this paper, the implications for converting a flip-flop based design to a latch-based design are investigated by performing timing and power analysis. Design flows are also proposed to convert a flip-flop based design to a latch-based design as well as a latch/flip-flop-mixed design. With a new retiming strategy, the optimum operating condition is identified for both the latch based design and the mixed design, where the maximum time borrowing or performance enhancement can be obtained. Compared to the flip-flop based design, 48% and 45% frequency boosting are achieved by the latch based design and the mixed design, respectively. While maintaining the same performance as the flip-flop based design with the aid of supply voltage scaling, the latch based design and the mixed design reduce the power consumption by 21% and 16%, respectively, in an industrial 28-nm FDSOI CMOS technology
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Multi-bit pulsed-latch based low power synchronous circuit design
IEEE Computer Society, 2018Co-Authors: Singh Kamlesh, Rosas, Omar Alejandro Rodriguez, Jiao Hailong, Huisken Jos, De Gyvez, José PinedaAbstract:Pulsed-latches emerge as an ideal sequencing element for low power digital circuit design, serving as an alternative of Flip-Flops. In this paper, low power multi-bit pulsed-latches are proposed to construct pipeline stages in synchronous digital circuits. A method of integrating the proposed multi-bit pulsed-latches in the commercial design flows is also introduced. With the multi-bit pulsed-latches, up to 45% power savings are achieved for a variety of ITC benchmark circuits and an ARM Cortex-M0 as compared to the flip-flop based designs in an industrial 28-nm FDSOI CMOS technology. Furthermore, the power consumption of the clock distribution network and the layout area are reduced by up to 83% and 16%, respectively, with the proposed multi-bit pulsed-latches as compared to the flip-flop based designs
Kk Singh - One of the best experts on this subject based on the ideXlab platform.
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Multi-bit pulsed-latch based low power synchronous circuit design
IEEE Computer Society, 2018Co-Authors: Kk Singh, Oa ,rodriguez Rosas, Jiao H Hailong, Huisken, Ja Jos, Pineda De Gyvez, J JoséAbstract:\u3cp\u3ePulsed-latches emerge as an ideal sequencing element for low power digital circuit design, serving as an alternative of Flip-Flops. In this paper, low power multi-bit pulsed-latches are proposed to construct pipeline stages in synchronous digital circuits. A method of integrating the proposed multi-bit pulsed-latches in the commercial design flows is also introduced. With the multi-bit pulsed-latches, up to 45% power savings are achieved for a variety of ITC benchmark circuits and an ARM Cortex-M0 as compared to the flip-flop based designs in an industrial 28-nm FDSOI CMOS technology. Furthermore, the power consumption of the clock distribution network and the layout area are reduced by up to 83% and 16%, respectively, with the proposed multi-bit pulsed-latches as compared to the flip-flop based designs.\u3c/p\u3
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Low power latch based design with smart retiming
IEEE Computer Society, 2018Co-Authors: Kk Singh, Jiao H Hailong, Huisken, Ja Jos, Fatemi, Sh Hamed, Pineda De Gyvez, J JoséAbstract:\u3cp\u3eFlip-Flops and latches are two options to construct pipelines in digital integrated circuits (ICs). In this paper, the implications for converting a flip-flop based design to a latch-based design are investigated by performing timing and power analysis. Design flows are also proposed to convert a flip-flop based design to a latch-based design as well as a latch/flip-flop-mixed design. With a new retiming strategy, the optimum operating condition is identified for both the latch based design and the mixed design, where the maximum time borrowing or performance enhancement can be obtained. Compared to the flip-flop based design, 48% and 45% frequency boosting are achieved by the latch based design and the mixed design, respectively. While maintaining the same performance as the flip-flop based design with the aid of supply voltage scaling, the latch based design and the mixed design reduce the power consumption by 21% and 16%, respectively, in an industrial 28-nm FDSOI CMOS technology.\u3c/p\u3
