The Experts below are selected from a list of 13131 Experts worldwide ranked by ideXlab platform
P. Hasler - One of the best experts on this subject based on the ideXlab platform.
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A Programmable Continuous-Time Floating-Gate
2020Co-Authors: Matt Kucic, P. Hasler, Joe NeffAbstract:We present a programmable continuous-time Floating-Gate Fourier processor that decomposes the incoming signal into frequency bands by analog bandpass filters, multiplies each channel by a nonvolitile weight, and then recombines the frequency channels. A digital signal processor would take a similar approach of computing a fast Fourier transform (FFT), multiplying the frequency components by a weight and then computing an inverse FFT. We decompose the frequency bands of the incoming signal using the transistor-only version of the autozeroing Floating-Gate amplifier (AFGA), also termed the capacitively coupled current conveyer (C ). Each band decom- position is then fed through a Floating-Gate multiplier to perform the band weighting. Finally, the multiplier outputs are summed using Kirchoff current law to give a band-weighted output of the original signal. We examine many options to reduce second-order harmonic problems inherent in the single-sided C. We present a method for programming arrays of Floating-Gate devices that are used in the weighting of the bands. All of these pieces fit together to form an elegant and systematic Fourier processor.
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Trapped charge characterization and removal on Floating-Gate transistors
2008 51st Midwest Symposium on Circuits and Systems, 2008Co-Authors: Brian Degnan, P. Hasler, Christopher M. TwiggAbstract:Floating-Gate transistors that have contacts to the lowest metal to the polysilicon Floating-Gate were fabricated to determine if the lowest metal flow alone could normalize charge across multiple Floating Gates. The metal contacts did not normalize charge for different numbers of contacts to polysilicon; however, a decreased variance of trapped charge was found when compared to polysilicon Floating-Gates that have no contacts to lowestmetal. The charge leakage from the Floating-Gate was negligible after one year, suggesting that layout may play a critical factor in leakage.
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A Floating-Gate-Based Programmable CMOS Reference
IEEE Transactions on Circuits and Systems I: Regular Papers, 2008Co-Authors: Venkatesh Srinivasan, Christopher M. Twigg, Guillermo Serrano, P. HaslerAbstract:We describe a compact programmable CMOS reference, where the reference is determined by the charge difference between two Floating-Gate transistors, thereby making the reference insensitive to temperature and other environmental effects. Using Floating-Gate transistors adds programmability making a wide range of reference voltages possible with negligible long-term drift. A prototype circuit has been implemented in a 0.35-mum CMOS process, and reference voltages ranging from 50 mV to 0.6 V have been achieved. We demonstrate a voltage reference programming accuracy of plusmn40 muV . Experimental results indicate a temperature sensitivity of approximately 53 muV/degC for a nominal reference voltage of 0.4 V over a temperature range of -60degC-140degC.
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IWSOC - Floating-Gate devices, circuits, and systems
Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05), 2005Co-Authors: P. HaslerAbstract:This paper describes our programmable analog technology based around Floating-Gate transistors that allow for non-volatile storage as well as computation through the same device. We describe the basic concepts for Floating-Gate devices, capacitor-based circuits, and the basic charge modification mechanisms that makes this analog technology programmable. We describe the techniques to extend these techniques to program an nonhomogenious array of Floating-Gate devices.
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An analog Floating-Gate node for Supervised learning
IEEE Transactions on Circuits and Systems, 2005Co-Authors: P. Hasler, J. DuggerAbstract:We present an improved analog Floating-Gate pFET synapse that implements a supervised learning algorithm similar to the least mean square (LMS) learning rule. Weight decay plays a key role in several learning rules; this Floating-Gate synapse exhibits this behavior. We examine implications of the weight decay appearing in the correlation learning rule realized in the Floating-Gate synapse and provide experimental data characterizing the synapse and its performance in one-input and two-input LMS networks. Analog Floating-Gate synapses will enable larger-scale, on-chip learning networks than previously possible.
Shantanu Chakrabartty - One of the best experts on this subject based on the ideXlab platform.
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Varactor-driven temperature compensation of CMOS Floating-Gate current memory
2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2012Co-Authors: Ming Gu, Shantanu ChakrabarttyAbstract:Floating-Gate transistors serve as an attractive media for non-volatile storage of analog parameters in neural systems. However, conventional current memories based on Floating-Gate transistors are sensitive to variations in temperature, therefore limiting their applications to only controlled environments. In this paper we propose a temperature compensated Floating-Gate array that can be programmed to store currents down to picoampere level. At the core of the proposed architecture is a control algorithm that uses a varactor to adapt the Floating-Gate capacitance such that the temperature dependent factors can be effectively canceled. As a result, the stored current is theoretically a function of a reference current and the differential charge stored on the Floating-Gates. We validate the proof-of-concept using measurement results obtained from prototype current memory cells fabricated in a 0.5μm CMOS process.
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ISCAS - Varactor-driven temperature compensation of CMOS Floating-Gate current memory
2012 IEEE International Symposium on Circuits and Systems, 2012Co-Authors: Ming Gu, Shantanu ChakrabarttyAbstract:Floating-Gate transistors serve as an attractive media for non-volatile storage of analog parameters in neural systems. However, conventional current memories based on Floating-Gate transistors are sensitive to variations in temperature, therefore limiting their applications to only controlled environments. In this paper we propose a temperature compensated Floating-Gate array that can be programmed to store currents down to picoampere level. At the core of the proposed architecture is a control algorithm that uses a varactor to adapt the Floating-Gate capacitance such that the temperature dependent factors can be effectively canceled. As a result, the stored current is theoretically a function of a reference current and the differential charge stored on the Floating-Gates. We validate the proof-of-concept using measurement results obtained from prototype current memory cells fabricated in a 0.5µm CMOS process.
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ISCAS - A temperature compensated array of CMOS Floating-Gate analog memory
Proceedings of 2010 IEEE International Symposium on Circuits and Systems, 2010Co-Authors: Chenling Huang, Shantanu ChakrabarttyAbstract:Floating-Gate transistors have been extensively used as analog memory elements in adaptive learning and neural systems. However, conventional techniques for storing and programming sub-threshold currents on Floating-Gate transistors are sensitive to temperature variations thus limiting their applicability to controlled environments. In this paper, we propose a temperature compensated Floating-Gate array which can be used to store and program currents down to nanoampere level. The core of the proposed current memory is a dual-channel Floating-Gate transistor based current reference circuit which uses a linear resistor in translinear loop. As a result the stored current is linearly proportional to the charge on the Floating-Gate and hence can be precisely programmed. The paper presents results from a prototype fabricated in a 0.5-µm CMOS process which validates the functionality of the proposed current memory cell.
Masud H Chowdhury - One of the best experts on this subject based on the ideXlab platform.
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Multilayer graphene nanoribbon Floating Gate transistor for flash memory
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014Co-Authors: Nahid M. Hossain, Masud H ChowdhuryAbstract:Floating Gate transistor is the basic building block of nonvolatile flash memory, which is one of the most widely used memory gadgets in modern micro and nano electronic applications. As silicon based integrated circuit technologies are approaching the limits of scaling, carbon based nanoelectronic devices are emerging as the future platform for low power, low cost, high performance and environment friendly circuits and systems. In this paper, a new concept of carbon nanostructure based Floating Gate transistor is presented. We have demonstrated a design using multilayer graphene nanoribbon (MLGNR) as the channel material and carbon nanotube (CNT) as the Floating Gate in the Floating Gate transistor. We have performed analysis of the charge accumulation mechanism in the Floating Gate and its dependence on the applied terminal voltages. We have observed that the proposed Floating Gate transistor can be operated at a much lower voltage compared to the conventional silicon based Floating Gate devices.
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ISCAS - Multilayer graphene nanoribbon Floating Gate transistor for flash memory
2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014Co-Authors: Nahid M. Hossain, Masud H ChowdhuryAbstract:Floating Gate transistor is the basic building block of nonvolatile flash memory, which is one of the most widely used memory gadgets in modern micro and nano electronic applications. As silicon based integrated circuit technologies are approaching the limits of scaling, carbon based nanoelectronic devices are emerging as the future platform for low power, low cost, high performance and environment friendly circuits and systems. In this paper, a new concept of carbon nanostructure based Floating Gate transistor is presented. We have demonstrated a design using multilayer graphene nanoribbon (MLGNR) as the channel material and carbon nanotube (CNT) as the Floating Gate in the Floating Gate transistor. We have performed analysis of the charge accumulation mechanism in the Floating Gate and its dependence on the applied terminal voltages. We have observed that the proposed Floating Gate transistor can be operated at a much lower voltage compared to the conventional silicon based Floating Gate devices.
Ming Gu - One of the best experts on this subject based on the ideXlab platform.
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Varactor-driven temperature compensation of CMOS Floating-Gate current memory
2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2012Co-Authors: Ming Gu, Shantanu ChakrabarttyAbstract:Floating-Gate transistors serve as an attractive media for non-volatile storage of analog parameters in neural systems. However, conventional current memories based on Floating-Gate transistors are sensitive to variations in temperature, therefore limiting their applications to only controlled environments. In this paper we propose a temperature compensated Floating-Gate array that can be programmed to store currents down to picoampere level. At the core of the proposed architecture is a control algorithm that uses a varactor to adapt the Floating-Gate capacitance such that the temperature dependent factors can be effectively canceled. As a result, the stored current is theoretically a function of a reference current and the differential charge stored on the Floating-Gates. We validate the proof-of-concept using measurement results obtained from prototype current memory cells fabricated in a 0.5μm CMOS process.
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ISCAS - Varactor-driven temperature compensation of CMOS Floating-Gate current memory
2012 IEEE International Symposium on Circuits and Systems, 2012Co-Authors: Ming Gu, Shantanu ChakrabarttyAbstract:Floating-Gate transistors serve as an attractive media for non-volatile storage of analog parameters in neural systems. However, conventional current memories based on Floating-Gate transistors are sensitive to variations in temperature, therefore limiting their applications to only controlled environments. In this paper we propose a temperature compensated Floating-Gate array that can be programmed to store currents down to picoampere level. At the core of the proposed architecture is a control algorithm that uses a varactor to adapt the Floating-Gate capacitance such that the temperature dependent factors can be effectively canceled. As a result, the stored current is theoretically a function of a reference current and the differential charge stored on the Floating-Gates. We validate the proof-of-concept using measurement results obtained from prototype current memory cells fabricated in a 0.5µm CMOS process.
C. Diorio - One of the best experts on this subject based on the ideXlab platform.
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an autozeroing Floating Gate amplifier
IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing, 2001Co-Authors: P. Hasler, B A Minch, C. DiorioAbstract:We have developed a bandpass Floating-Gate amplifier that uses tunneling and pFET hot-electron injection to set its dc operating point adaptively. Because the hot-electron injection is an inherent part of the pFET's behavior, we obtain this adaptation with no additional circuitry. Because the Gate currents are small, the circuit exhibits a high-pass characteristic with a cutoff frequency less than 1 Hz. The high-frequency cutoff is controlled electronically, as is done in continuous-time filters. We have derived analytical models that completely characterize the amplifier and that are in good agreement with experimental data for a wide range of operating conditions and input waveforms. This autozeroing Floating-Gate amplifier demonstrates how to use continuous-time Floating-Gate adaptation in amplifier design.
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ISCAS (2) - Floating-Gate devices: they are not just for digital memories any more
ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349), 1999Co-Authors: P. Hasler, B.a. Minch, C. DiorioAbstract:Since the first reported Floating-Gate structure in 1967, Floating-Gate transistors have been used widely to store digital information for long periods in structures such as EPROMs and EEPROMs. Recently Floating-Gate devices have found applications as analog memories, analog and digital circuit elements, and adaptive processing elements. Floating-Gate devices have found commerical applications, e.g. ISD, for long-term non-volatile information storage devices for analog applications. The focus of Floating-Gate devices has been towards fabrication in standard CMOS processes, as opposed to the specialized processes for fabricating digital non-volatile memories. Floating-Gate circuits can be designed at any or all of three levels: analog memory elements, capacitive-based circuit elements, and adaptive circuit elements.
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Adaptive circuits using pFET Floating-Gate devices
Proceedings 20th Anniversary Conference on Advanced Research in VLSI, 1999Co-Authors: P. Hasler, B.a. Minch, C. DiorioAbstract:In this paper, we describe our Floating-Gate pFET device, with its many circuit applications and supporting experimental measurements. We developed these devices in standard double-poly CMOS technologies by utilizing many effects inherent in these processes. We add Floating-Gate charge by electron tunneling, and we remove Floating-Gate charge by hot-electron injection. With this Floating-Gate technology, we cannot only build analog EEPROMs, we can also implement adaptation and learning when we consider Floating-Gate devices to be circuit elements with important time-domain dynamics. We start by discussing non-adaptive properties of Floating-Gate devices and we present two representative non-adaptive applications. First, we discuss using the Floating-Gate pFETs as non-volatile voltage sources or potentiometers (e-pots). Second, we discuss using Floating-Gate pFETs to build translinear circuits that compute the product of powers of the input currents. We then discuss the physics, behavior, and applications of adaptation using Floating-Gate pFETs. The physics of adaptation starts with Floating-Gate pFETs with continuous tunneling and injection currents. A single Floating-Gate MOS device operating with continuous-time tunneling and injection currents can exhibit either stabilizing or destabilizing behaviors. One particular application is an autozeroing Floating-Gate amplifier (AFGA) that uses tunneling and pFET hot-electron injection to adaptively set its DC operating point. Continuous-time circuits comprising multiple Floating-Gate MOS devices show various competitive and cooperative behaviors between devices. These Floating-Gate circuits can be used to build silicon systems that adapt and learn.
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ARVLSI - Adaptive circuits using pFET Floating-Gate devices
Proceedings 20th Anniversary Conference on Advanced Research in VLSI, 1999Co-Authors: P. Hasler, B.a. Minch, C. DiorioAbstract:In this paper, we describe our Floating-Gate pFET device, with its many circuit applications and supporting experimental measurements. We developed these devices in standard double-poly CMOS technologies by utilizing many effects inherent in these processes. We add Floating-Gate charge by electron tunneling, and we remove Floating-Gate charge by hot-electron injection. With this Floating-Gate technology, we cannot only build analog EEPROMs, we can also implement adaptation and learning when we consider Floating-Gate devices to be circuit elements with important time-domain dynamics. We start by discussing non-adaptive properties of Floating-Gate devices and we present two representative non-adaptive applications. First, we discuss using the Floating-Gate pFETs as non-volatile voltage sources or potentiometers (e-pots). Second, we discuss using Floating-Gate pFETs to build translinear circuits that compute the product of powers of the input currents. We then discuss the physics, behavior, and applications of adaptation using Floating-Gate pFETs. The physics of adaptation starts with Floating-Gate pFETs with continuous tunneling and injection currents. A single Floating-Gate MOS device operating with continuous-time tunneling and injection currents can exhibit either stabilizing or destabilizing behaviors. One particular application is an autozeroing Floating-Gate amplifier (AFGA) that uses tunneling and pFET hot-electron injection to adaptively set its DC operating point. Continuous-time circuits comprising multiple Floating-Gate MOS devices show various competitive and cooperative behaviors between devices. These Floating-Gate circuits can be used to build silicon systems that adapt and learn.
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Floating-Gate MOS synapse transistors
The Springer International Series in Engineering and Computer Science, 1998Co-Authors: C. Diorio, P. Hasler, B.a. Minch, Carver A. MeadAbstract:Our goal is to develop silicon learning systems. One impediment to achieving this goal has been the lack of a simple circuit element combining nonvolatile analog memory storage with locally computed memory updates. Existing circuits [63, 132] typically are large and complex; the nonvolatile Floating-Gate devices, such as EEPROM transistors, typically are optimized for binary-valued storage [17], and do not compute their own memory updates. Although Floating-Gate transistors can provide nonvolatile analog storage [1, 15], because writing the memory entails the difficult process of moving electrons through SiO2, these devices have not seen wide use as memory elements in silicon learning systems.