The Experts below are selected from a list of 327 Experts worldwide ranked by ideXlab platform
Paul P Sotiriadis - One of the best experts on this subject based on the ideXlab platform.
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single bit all digital Frequency Synthesis using homodyne sigma delta modulation
IEEE Transactions on Ultrasonics Ferroelectrics and Frequency Control, 2017Co-Authors: Paul P SotiriadisAbstract:All-digital Frequency Synthesis using bandpass sigma-delta modulation to achieve spectrally clean single-bit output is presented and mathematically analyzed resulting in a complete model to predict the stability and output spectrum. The quadrature homodyne filter architecture is introduced resulting in efficient implementations of carrier-Frequency-centered bandpass filters for the modulator. A multiplierless version of the quadrature homodyne filter architecture is also introduced to reduce complexity while maintaining a clean in-band spectrum. MATLAB and SIMULINK simulation results present the potential capabilities of the synthesizer architectures and validate the accuracy of the developed theoretical framework.
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ISCAS - Single-bit all digital Frequency Synthesis with homodyne sigma-delta modulation for Internet of Things applications
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017Co-Authors: Paul P Sotiriadis, Charis BasetasAbstract:All-digital Frequency Synthesis architectures with direct modulation capability, based on single-bit sigma-delta modulation loop with an innovative homodyne band-pass filter topology are presented focusing on wireless Internet of Things (IoT) applications. A hardware-efficient multiplier-free variation of the homodyne filter is also proposed. MATLAB simulation results for 16-QAM modulation demonstrate the capabilities of the proposed architectures.
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direct all digital Frequency Synthesis techniques spurs suppression and deterministic jitter correction
IEEE Transactions on Circuits and Systems, 2012Co-Authors: Paul P Sotiriadis, Kostas GalanopoulosAbstract:Direct all-digital Frequency synthesizers are favored by modern nanoscale CMOS technologies but suffer from strong Frequency spurs and timing irregularities. To counter these drawbacks various jitter-correction and spurs-suppression techniques have been proposed. This paper presents a comprehensive literature review and a comparative study of such techniques, applied to popular direct all-digital Frequency Synthesis cores, identifying their strengths and weaknesses.
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Cascaded Diophantine Frequency Synthesis
IEEE Transactions on Circuits and Systems I: Regular Papers, 2008Co-Authors: Paul P SotiriadisAbstract:Cascaded diophantine Frequency Synthesis (CDFS) is an approach to high-resolution Frequency Synthesis based on the mathematical properties of integer numbers and diophantine equations. CDFS can be implemented using two or more phase-locked loops (PLLs) and Frequency mixing stages in a cascade topology. CDFS achieves Frequency resolution arbitrarily finer than that of the constituent PLLs while maintaining their loop bandwidths and Frequency hopping agility. CDFS results in intermediate signals with minimal Frequency ranges in all Frequency mixing stages, allowing for improved spectral purity and lower design complexity compared to the parallel form of its predecessor, diophantine Frequency Synthesis (DFS). CDFS architectures are modularly structured and expandable. The paper introduces CDFS focusing on the mathematical and algorithmic aspects.
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Principles of Cascaded Diophantine Frequency Synthesis
2008 IEEE International Frequency Control Symposium, 2008Co-Authors: Paul P SotiriadisAbstract:Cascaded diophantine Frequency Synthesis (CDFS) is a new systematic methodology for developing and programming modular multi-loop Frequency synthesizers with high Frequency resolution, fast Frequency hopping and potentially very low spurs, especially near-in. CDFS results in significantly reduced Frequency ranges of the intermediate signals in the Frequency mixing stages compared to the predecessor, diophantine Frequency Synthesis methodology. This simplifies the design and Frequency planing for the synthesizer and allows for improved spectral purity of the output signal.
Thomas H. Lee - One of the best experts on this subject based on the ideXlab platform.
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a multiply by 3 coupled ring oscillator for low power Frequency Synthesis
IEEE Journal of Solid-state Circuits, 2004Co-Authors: S. Verma, Thomas H. LeeAbstract:A Frequency-Synthesis technique which extracts the Nth harmonic from an N-stage oscillator is presented. This technique enables significant power savings in the prescaler of a Frequency synthesizer. The maximum achievable voltage swing from such an oscillator is estimated. To study this technique, a multiply-by-3 circuit with two 180/spl deg/-coupled single-ended three-stage ring oscillators has been fabricated in 0.24-/spl mu/m CMOS, designed to work in the 902-928-MHz ISM band (U.S. and Canada). It provides two outputs: one at the normal operating Frequency of the oscillator and the other at three times that Frequency. The circuit can work at voltages as low as 1.3 V, while consuming 210 /spl mu/A of current.
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Multi-GHz Frequency Synthesis & Division: Frequency Synthesizer Design for 5 GHz Wireless LAN Systems
2001Co-Authors: Hamid R. Rategh, Thomas H. LeeAbstract:There has been an increasing demand for Wireless Local Area Network (WLAN) systems in the past few years. New Frequency bands are allocated and new standards are being developed to accommodate higher data rates. The fast trend of CMOS scaling has provided an opportunity for the development of low cost integrated WLAN systems. Frequency synthesizers are one of the main building blocks of wireless transceivers. The high Frequency digital Frequency dividers in a phase-locked loop (PLL) based Frequency synthesizer are among the most challenging blocks to design and usually account for a large percentage of the synthesizer total power dissipation. The successful design and integration of a high Frequency PLL demands a comprehensive understanding of wireless systems, RF circuits, and loop stability issues. Multi-GHz Frequency Synthesis & Division starts with an overview of WLAN systems and reviews the WLAN market and standards. It then studies PLLs as an essential building block of WLAN receivers, and provides guidelines and engineering recipes for the design of loop filters in high Frequency PLLs. Additionally, the book investigates different analog and digital Frequency division techniques and introduces injection-locked Frequency dividers (ILFDs) as an alternative for conventional Frequency dividers. Finally, the book demonstrates a successful design of a fully integrated CMOS Frequency synthesizer for a 5 GHz WLAN receiver. Multi-GHz Frequency Synthesis & Division will be of interest to RF and high-speed analog circuit designers and students as well as wireless engineers.
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A multiply-by-3 coupled-ring oscillator for low-power Frequency Synthesis
2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408), 1Co-Authors: S. Verma, Thomas H. LeeAbstract:A Frequency-Synthesis technique which extracts the N/sup th/ harmonic from an N-stage oscillator is presented. The maximum achievable voltage swing from such an oscillator is estimated. To study this technique, a multiply-by-3 circuit with two 180/spl deg/-coupled, single-ended three-stage ring oscillators has been fabricated in 0.24 /spl mu/m CMOS, designed to work in the 902-928 MHz ISM band (US and Canada). It provides two outputs: one at the normal operating Frequency of the oscillator, and another at three times that Frequency. The circuit can work at voltages as low as 1.3 V, while consuming 210 /spl mu/A of current.
Harald R. Telle - One of the best experts on this subject based on the ideXlab platform.
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Four-wave mixing in laser diodes for difference-Frequency Synthesis
Journal of the Optical Society of America B, 1996Co-Authors: Ch. Koch, Harald R. TelleAbstract:Laser diodes are not only good laser-light sources but highly efficient nonlinear elements. The mixing signal power as a function of pump Frequency differences of as much as 3 THz for three- and four-color four-wave mixing configurations is investigated experimentally and theoretically. The influence of phase matching, mode-spacing dispersion, and resonance effects is described by a round-trip model yielding an effective nonlinearity from the experimental data. The values obtained are in good agreement with the theoretical results. The phase-coherent bisection of a Frequency interval and heterodyne detection with a coherent local oscillator are demonstrated as examples of application of four-wave mixing in laser diodes in Frequency Synthesis and spectroscopy.
Pierre Vincent - One of the best experts on this subject based on the ideXlab platform.
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A 4.596 GHz Frequency Synthesis based on a solid-mounted resonator
2011 Joint Conference of the IEEE International Frequency Control and the European Frequency and Time Forum (FCS) Proceedings, 2011Co-Authors: Rodolphe Boudot, Ming-dong Li, Nathalie Rolland, Paul-alain Rolland, Vincent Giordano, Pierre VincentAbstract:We report a 4.596 GHz Frequency Synthesis based on a 2.1 GHz Solid Mounted Resonator (SMR) voltage controlled oscillator (VCO). The SMR source exhibits a power consumption of about 18 mW, a chip size of 2mm2 and a phase noise of - 89 dBc/Hz at 2 kHz offset Frequency. A synthesizer is constructed from this source to generate a low noise 4.596 GHz signal. The synthesizer is preliminary used as a local oscillator in a compact Cs atomic clock based on Coherent Population Trapping (CPT).
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A solid-mounted resonator-oscillator-based 4.596 GHz Frequency Synthesis
Review of Scientific Instruments, 2011Co-Authors: Rodolphe Boudot, Nathalie Rolland, Vincent Giordano, P. A. Rolland, Pierre VincentAbstract:This paper describes a 4.596 GHz Frequency Synthesis based on a 2.1 GHz solid mounted resonator (SMR) voltage-controlled oscillator (VCO). The SMR oscillator presents a chip size lower than 2 mm(2), a power consumption of 18.2 mW, and exhibits a phase noise of -89 dBc/Hz and -131 dBc/Hz at 2 kHz and 100 kHz offset frequencies, respectively. The VCO temperature-Frequency dependence is measured to be -14 ppm/degrees C over a range of -20 degrees C to 60 degrees C. From this source, a low noise Frequency synthesizer is developed to generate a 4.596 GHz signal (half of the Cs atom hyperfine transition Frequency) with a phase noise of -81 dBc/Hz and -120 dBc/Hz at 2 kHz and 100 kHz from the carrier. The Frequency Synthesis output is used as a local oscillator in a Cs vapor microcell-based compact atomic clock. Preliminary results are reported and discussed. To the authors knowledge, this is the first development of a SMR-oscillator-based Frequency synthesizer for miniature atomic clocks applications.
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A solid-mounted resonator-oscillator-based 4.596 GHz Frequency Synthesis.
The Review of scientific instruments, 2011Co-Authors: Rodolphe Boudot, Nathalie Rolland, Paul-alain Rolland, Vincent Giordano, Pierre VincentAbstract:This paper describes a 4.596 GHz Frequency Synthesis based on a 2.1 GHz solid mounted resonator (SMR) voltage-controlled oscillator (VCO). The SMR oscillator presents a chip size lower than 2 mm2, a power consumption of 18.2 mW, and exhibits a phase noise of −89 dBc/Hz and −131 dBc/Hz at 2 kHz and 100 kHz offset frequencies, respectively. The VCO temperature–Frequency dependence is measured to be −14 ppm/°C over a range of −20 ○C to 60 ○C. From this source, a low noise Frequency synthesizer is developed to generate a 4.596 GHz signal (half of the Cs atom hyperfine transition Frequency) with a phase noise of −81 dBc/Hz and −120 dBc/Hz at 2 kHz and 100 kHz from the carrier. The Frequency Synthesis output is used as a local oscillator in a Cs vapor microcell-based compact atomic clock. Preliminary results are reported and discussed. To the authors knowledge, this is the first development of a SMR-oscillator-based Frequency synthesizer for miniature atomic clocks applications.
S. Verma - One of the best experts on this subject based on the ideXlab platform.
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a multiply by 3 coupled ring oscillator for low power Frequency Synthesis
IEEE Journal of Solid-state Circuits, 2004Co-Authors: S. Verma, Thomas H. LeeAbstract:A Frequency-Synthesis technique which extracts the Nth harmonic from an N-stage oscillator is presented. This technique enables significant power savings in the prescaler of a Frequency synthesizer. The maximum achievable voltage swing from such an oscillator is estimated. To study this technique, a multiply-by-3 circuit with two 180/spl deg/-coupled single-ended three-stage ring oscillators has been fabricated in 0.24-/spl mu/m CMOS, designed to work in the 902-928-MHz ISM band (U.S. and Canada). It provides two outputs: one at the normal operating Frequency of the oscillator and the other at three times that Frequency. The circuit can work at voltages as low as 1.3 V, while consuming 210 /spl mu/A of current.
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A multiply-by-3 coupled-ring oscillator for low-power Frequency Synthesis
2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408), 1Co-Authors: S. Verma, Thomas H. LeeAbstract:A Frequency-Synthesis technique which extracts the N/sup th/ harmonic from an N-stage oscillator is presented. The maximum achievable voltage swing from such an oscillator is estimated. To study this technique, a multiply-by-3 circuit with two 180/spl deg/-coupled, single-ended three-stage ring oscillators has been fabricated in 0.24 /spl mu/m CMOS, designed to work in the 902-928 MHz ISM band (US and Canada). It provides two outputs: one at the normal operating Frequency of the oscillator, and another at three times that Frequency. The circuit can work at voltages as low as 1.3 V, while consuming 210 /spl mu/A of current.
