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Maheshwari S. - One of the best experts on this subject based on the ideXlab platform.
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Modelling, Simulation and Verification of 4-phase Adiabatic Logic Design: A VHDL-Based Approach
'Elsevier BV', 2019Co-Authors: Maheshwari S.Abstract:The design and Functional verification of the 4-phase adiabatic logic implementation take longer due to the complexity of synchronizing the power-clock phases. Additionally, as the adiabatic system scales, the amount of time in debugging errors increases, thus, increasing the overall design and verification time. This paper proposes a VHDL-based modelling approach for speeding up the design and verification time of the 4-phase adiabatic logic systems. The proposed approach can detect the Functional errors, allowing the designer to correct them at an early design stage, leading to substantial reduction of the design and debugging time. The originality of this approach lies in the realization of the trapezoidal power-clock using Function Declaration for the four periods namely; Evaluation (E), Hold (H), Recovery (R) and Idle (I) exclusively. The four periods are defined in a VHDL package followed by a library design which contains the behavioral VHDL model of adiabatic NOT/BUF logic gate. Finally, this library is used to model and verify the structural VHDL representations of the 4-phase 2-bit ring-counter and 3-bit up-down counter, as design examples to demonstrate the practicality of the proposed approach
Shi Lusheng - One of the best experts on this subject based on the ideXlab platform.
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traps in the c Function Declaration
Techniques of Automation and Applications, 2005Co-Authors: Shi LushengAbstract:According to analyzing the reasons of four kinds of phenomena of two traps in C Function Declaration,the sources of the malFunctions are outlined.It should be paid attention to these problems while using traditional and modern Function Declarations.
Samir Palnitkar - One of the best experts on this subject based on the ideXlab platform.
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verilog hdl a guide to digital design and synthesis
1996Co-Authors: Samir PalnitkarAbstract:PART I. BASIC VERILOG TOPICS. 1. Overview of Digital Design with Verilog HDL. Evolution of Computer Aided Digital Design. Emergence of HDLs. Typical Design Flow. Importance of HDLs. Popularity of Verilog HDL. Trends in HDLs. 2. Hierarchical Modeling Concepts. Design Methodologies. 4-bit Ripple Carry Counter. Modules. Instances. Components of a Simulation. Example. Design Block. Stimulus Block. Summary. Exercises. 3. Basic Concepts. Lexical Conventions. Whitespace. Comments. Operators. Number Specification. Sized numbers. Unsized numbers. X or Z values. Negative numbers. Underscore characters and question marks. Strings. Identifiers and Keywords. Escaped Identifiers. Data Types. Value Set. Nets. Registers. Vectors. Integer , Real, and Time Register Data Types. Integer. Real Time. Arrays. Memories. Parameters. Strings. System Tasks and Compiler Directives. System Tasks. Displaying information. Monitoring information. Stopping and finishing in a simulation. Compiler Directives. 'define. 'include. Summary. Exercises. 4. Modules and Ports. Modules. Ports. List of Ports. Port Declaration. Port Connection Rules. Inputs. Outputs. Inouts. Width matching. Unconnected ports. Example of illegal port connection. Connecting Ports to External Signals. Connecting by ordered list. Connecting ports by name. Hierarchical Names. Summary. Exercises. 5. Gate-Level Modeling. Gate Types. And/Or Gates. Buf/Not Gates. Bufif/notif. Examples. Gate-level multiplexer. 4-bit full adder. Gate Delays. Rise, Fall, and Turn-off Delays. Rise delay. Fall delay. Turn-off delay. Min/Typ/Max Values. Min value. Typ val. Max value. Delay Example. Summary. Exercises. 6. Dataflow Modeling. Continuous Assignments. Implicit Continuous Assignment. Delays. Regular Assignment Delay. Implicit Continuous Assignment Delay. Net Declaration Delay. Expressions, Operators, and Operands. Expressions. Operands. Operators. Operator Types. Arithmetic Operators. Binary operators. Unary operators. Logical Operators. Relational Operators. Equality Operators. Bitwise Operators. Reduction Operators. Shift Operators. Concatenation Operator. Replication Operator. Conditional Operator. Operator Precedence. Examples. 4-to-1 Multiplexer. Method 1: logic equation. Method 2: conditional operator. 4-bit Full Adder. Method 1: dataflow operators. Method 2: full adder with carry lookahead. Ripple Counter. Summary. Exercises. 7. Behavioral Modeling. Structured Procedures. Initial Statement. Always Statement. Procedural Assignments. Blocking assignments. Nonblocking Assignments. Application of nonblocking assignments. Timing Controls. Delay-Based Timing Control. Regular delay control. Intra-assignment delay control. Zero delay control. Event-Based Timing Control. Regular event control. Named event control. Event OR control. Level-Sensitive Timing Control. Conditional Statements. Multiway Branching. Case Statement. Casex, casez Keywords. Loops. While Loop. For Loop. Repeat Loop. Forever loop. Sequential and Parallel Blocks. Block Types. Sequential blocks. Parallel blocks. Special Features of Blocks. Nested blocks. Named blocks. Disabling named blocks. Examples. 4-to-1 Multiplexer. 4-bit Counter. Traffic Signal Controller. Specification. Stimulus. Summary. Exercises. 8. Tasks and Functions. Differences Between Tasks and Functions. Tasks. Task Declaration and Invocation. Task Examples. Use of Input and Output Arguments. Asymmetric Sequence Generator. Functions. Function Declaration and Invocation. Function Examples. Parity calculation. Left/right shifter. Summary. Exercises. 9. Useful Modeling Techniques. Procedural Continuous Assignments. Assign and deassign. Force and release. Force and release on registers. Force and release on nets. Overriding Parameters. Defparam Statement. Module_Instance Parameter Values. Conditional Compilation and Execution. Conditional Compilation. Conditional Execution. Time Scales. Useful System Tasks. File Output. Opening a file. Writing to files. Closing files. Displaying Hierarchy. Strobing. Random Number Generation. Initializing Memory from File. Value Change Dump File. Summary. Exercises. PART II. ADVANCED VERILOG TOPICS. 10. Timing and Delays. Types of Delay Models. Distributed Delay. Lumped Delay. Pin-to-Pin Delays. Path Delay Modeling. Specify Blocks. Inside Specify Blocks. Parallel Connection. Full Connection. Specparam Statements. Conditional Path Delays. Rise, fall, and turn-off delays. Min, max, and typical delays. Handling x transitions. Timing Checks. $setup and $hold checks. $setup task. $hold task. $width Check. Delay Back-Annotation. Summary. Exercises. 11. Switch-Level Modeling. Switch-Modeling Elements. MOS Switches. CMOS Switches. Directional Switches. Power and Ground. Resistive Switches. Delay Specification on Switches. MOS and CMOS switches. Bidirectional pass switches. Specify blocks. Examples. CMOS Nor Gate. 2-to-1 Multiplexer. Simple CMOS Flip-Flop. Summary. Exercises. 12. User-Defined Primitives. UDP Basics. Parts of UDP Definition. UDP Rules. Combinational UDPs. Combinational UDP Definition. State Table Entries. Shorthand Notation for Don't Cares. Instantiating UDP Primitives. Example of a Combinational UDP. Sequential UDPs. Level-Sensitive Sequential UDPs. Edge-Sensitive Sequential UDPs. Example of a Sequential UDP. UDP Table Shorthand Symbols. Guidelines for UDP Design. Summary. Exercises. 13. Programming Language Interface. Uses of PLI. Linking and Invocation of PLI Tasks. Linking PLI Tasks. Linking PLI in Verilog-XL. Linking in VCS. Invoking PLI Tasks. General Flow of PLI Task Addition and Invocation. Internal Data Representation. PLI Library Routines. Access Routines. Mechanics of Access Routines. Types of Access Routines. Examples of Access Routines. Utility Routines. Mechanics of Utility Routines. Types of Utility Routines. Example of Utility Routines. Summary. Exercises. 14. Logic Synthesis with Verilog HDL. What Is Logic Synthesis? Impact of Logic Synthesis. Verilog HDL Synthesis. Verilog Constructs. Verilog Operators. Interpretation of a Few Verilog Constructs. The Assign statement. The if-else statement. The case statement for loops. The Function Statement. Synthesis Design Flow. RTL to Gates. RTL Description. Translation. Unoptimized Intermediate Representation. Logic Optimization. Technology Mapping and Optimization. Technology library. Design constraints. Optimized gate-level description. An Example of RTL-to-Gates. Design Sspecification. RTL description. Technology library. Design constraints. Logic synthesis. Final, Optimized, Gate-Level Description. IC Fabrication. Verification of Gate-Level Netlist. Functional Verification. Timing Verification. Modeling Tips for Logic Synthesis. Verilog Coding Style. Use meaningful names for signals and variables. Avoid mixing positive and negative edge-triggered flip-flops. Use basic building blocks vs. Use continuous assign statements. Instantiate multiplexers vs. Use if-else or case statements. Use parentheses to optimize logic structure. Use arithmetic operators *, /, and % vs. Design building blocks. Be careful with multiple assignments to the same variable. Define if-else or case statements explicitly. Design Partitioning. Horizontal partitioning. Vertical Partitioning. Parallelizing design structure. Design Constraint Specification. Example of Sequential Circuit Synthesis. Design Specification. Circuit Requirements. Finite State Machine (FSM). Verilog Description. Technology Library. Design Constraints. Logic Synthesis. Optimized Gate-Level Netlist. Verification. Summary. Exercises. PART III: APPENDICES. A. Strength Modeling and Advanced Net Definitions. B. List of PLI Routines. C. List of Keywords, System Tasks, and Compiler Directives. D. Formal Syntax Definition. E. Verilog Tidbits. F. Verilog Examples. Index.
Cavanagh Joseph - One of the best experts on this subject based on the ideXlab platform.
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Verilog HDL: digital design and modeling
'Informa UK Limited', 2007Co-Authors: Cavanagh JosephAbstract:PREFACE INTRODUCTION History of HDL Verilog HDL IEEE Standard Features Assertion Levels OVERVIEW Design Methodologies Modulo-16 Synchronous Counter Four-Bit Ripple Adder Modules and Ports Designing a Test Bench for Simulation Construct Definitions Introduction to Dataflow Modeling Two-Input Exclusive-OR Gate Four 2-Input AND Gates With Delay Introduction to Behavioral Modeling Three-Input OR Gate Four-Bit Adder Modulo-16 Synchronous Counter Introduction to Structural Modeling Sum-of-Products Implementation Full Adder Four-Bit Ripple Adder Introduction to Mixed-Design Modeling Full Adder Problems LANGUAGE ELEMENTS Comments Identifiers Keywords Bidirectional Gates Charge Storage Strengths CMOS Gates Combinational Logic Gates Continuous Assignment Data Types Module Declaration MOS Switches Multiple-Way Branching Named Event Parameters Port Declaration Procedural Constructs Procedural Continuous Assignment Procedural Flow Control Pull Gates Signal Strengths Specify Block Tasks and Functions Three-State Gates Timing Control User-Defined Primitives Value Set Data Types Net Data Types Register Data Types Compiler Directives Problems EXPRESSIONS Operands Constant Parameter Net Register Bit-Select Part-Select Memory Element Operators Arithmetic Logical Relational Equality Bitwise Reduction Shift Conditional Concatenation Replication Problems GATE-LEVEL MODELING Multiple-Input Gates Gate Delays Inertial Delay Transport Delay Module Path Delay Additional Design Examples Iterative Networks Priority Encoder Problems USER-DEFINED PRIMITIVES Defining a User-Defined Primitive Combinational User-Defined Primitives Map-Entered Variables Sequential User-Defined Primitives Level-Sensitive User-Defined Primitives Edge-Sensitive User-Defined Primitives Problems DATAFLOW MODELINGContinuous Assignment Three-Input AND Gate Sum Of Products Reduction Operators Octal-To-Binary Encoder Four-To-One Multiplexer Four-To-One Multiplexer Using The Conditional Operator Four-Bit Adder Carry Lookahead Adder Asynchronous Sequential Machine Pulse-Mode Asynchronous Sequential Machine Implicit Continuous Assignment Delays Problems BEHAVIORAL MODELINGProcedural Constructs Initial Statement Always Statement Procedural Assignments Intrastatement Delay Interstatement Delay Blocking Assignments Nonblocking Assignments Conditional Statement Case Statement Loop Statements For Loop While Loop Repeat Loop Forever Loop Block Statements Sequential Blocks Parallel Blocks Procedural Continuous Assignment Assign . . . Deassign Force . . . Release Problems STRUCTURAL MODELING Module Instantiation Ports Unconnected Ports Port Connection Rules Design Examples Gray-To-Binary Code Converter BCD-To-Decimal Decoder Modulo-10 Counter Adder/Subtractor Four-Function ALU Adder and High-Speed Shifter Array Multiplier Moore-Mealy Synchronous Sequential Machine Moore Synchronous Sequential Machine Moore Asynchronous Sequential Machine Moore Pulse-Mode Asynchronous Sequential Machine Problems TASKS AND FunctionS Tasks Task Declaration Task Invocation Functions Function Declaration Function Invocation Problems ADDITIONAL DESIGN EXAMPLES Johnson Counter Counter-Shifter Universal Shift Register Hamming Code Error Detection and Correction Booth Algorithm Moore Synchronous Sequential Machine Mealy Pulse-Mode Asynchronous Sequential Machine Mealy One-Hot Machine BCD Adder/Subtractor BCD Addition BCD Subtraction Pipelined RISC Processor Instruction Cache Instruction Unit Decode Unit Execution Unit Register File Data Cache RISC CPU Top System Top Problems APPENDIX A Event Queue Event Handling for Dataflow Constructs Event Handling for Blocking Assignments Event Handling for Nonblocking Assignments Event Handline for Mixed Blocking and Nonblocking Assignments APPENDIX B Verilog Project Procedure APPENDIX C Answers to Selected Problems Overview Language Elements Expressions Gate Level Modeling User-Defined Primitives Dataflow Modeling Behavioral Modeling Structural Modeling Tasks and Functions Additional Design Examples INDEX
Beling Piotr - One of the best experts on this subject based on the ideXlab platform.
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C++11 - okre\'slanie typ\'ow
2013Co-Authors: Beling PiotrAbstract:This paper presents a review of some new futures introduced to C++ language by ISO/IEC 14882:2011 standard (known as C++11). It describes new language elements which allow to easier expressed of types of variables: auto and decltype keywords, new Function Declaration syntax, and tools which are included in type_traits header. ----- Niniejszy artyku{\l} jest jednym z serii artyku{\l}\'ow w kt\'orych zawarto przegl{\ka}d nowych element\'ow j{\ke}zyka C++ wprowadzonych przez standard ISO/IEC 14882:2011, znany pod nazw{\ka} C++11. W artykule przedstawiono nowe mo\.zliwo\'sci zwi{\ka}zane ze wskazywaniem typ\'ow zmiennych. Opisano s{\l}owa kluczowe auto i decltype, now{\ka} sk{\l}adnie deklarowania funkcji/metod oraz narz{\ke}dzia zawarte w pliku nag{\l}\'owkowym .Comment: 6 pages, in Polis
