The Experts below are selected from a list of 321 Experts worldwide ranked by ideXlab platform
Pranav Ashar - One of the best experts on this subject based on the ideXlab platform.
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a fast inexpensive and scalable hardware acceleration technique for Functional Simulation
Design Automation Conference, 2002Co-Authors: Srihari Cadambi, Chandra Mulpuri, Pranav AsharAbstract:We introduce a novel approach to accelerating Functional Simulation. The key attributes of our approach are high-performance, low-cost, scalability and low turn-around-time (TAT). We achieve speedups between 25 and 2000x over zero delay event-driven Simulation and between 75 and 1000x over cycle-based Simulation on benchmark and industrial circuits while maintaining the cost, scalability and TAT advantages of Simulation. Owing to these attributes, we believe that such an approach has potential for very wide deployment as replacement or enhancement for existing simulators. Our technology relies on a VLIW-like virtual Simulation processor (SimPLE) mapped to a single FPGA on an off-the-shelf PCI board. Primarily responsible for the speed are (i) parallelism in the processor architecture (ii) high pin count on the FPGA enabling large instruction bandwidth and (iii) high speed (124 MHz on Xilinx Virtex-II) single-FPGA implementation of the processor with regularity driven efficient place and route. Companion to the processor is the very fast SimPLE compiler which achieves compilation rates of 4 million gates/hour. In order to simulate the netlist, the compiled instructions are streamed through the FPGA, along with the Simulation vectors. This architecture plugs in naturally into any existing HDL Simulation environment. We have a working prototype based on a commercially available PCI-based FPGA board.
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DAC - A fast, inexpensive and scalable hardware acceleration technique for Functional Simulation
Proceedings of the 39th conference on Design automation - DAC '02, 2002Co-Authors: Srihari Cadambi, Chandra Mulpuri, Pranav AsharAbstract:We introduce a novel approach to accelerating Functional Simulation. The key attributes of our approach are high-performance, low-cost, scalability and low turn-around-time (TAT). We achieve speedups between 25 and 2000x over zero delay event-driven Simulation and between 75 and 1000x over cycle-based Simulation on benchmark and industrial circuits while maintaining the cost, scalability and TAT advantages of Simulation. Owing to these attributes, we believe that such an approach has potential for very wide deployment as replacement or enhancement for existing simulators. Our technology relies on a VLIW-like virtual Simulation processor (SimPLE) mapped to a single FPGA on an off-the-shelf PCI board. Primarily responsible for the speed are (i) parallelism in the processor architecture (ii) high pin count on the FPGA enabling large instruction bandwidth and (iii) high speed (124 MHz on Xilinx Virtex-II) single-FPGA implementation of the processor with regularity driven efficient place and route. Companion to the processor is the very fast SimPLE compiler which achieves compilation rates of 4 million gates/hour. In order to simulate the netlist, the compiled instructions are streamed through the FPGA, along with the Simulation vectors. This architecture plugs in naturally into any existing HDL Simulation environment. We have a working prototype based on a commercially available PCI-based FPGA board.
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fast Functional Simulation using branching programs
International Conference on Computer Aided Design, 1995Co-Authors: Pranav Ashar, Sharad MalikAbstract:Abstract: This paper addresses the problem of speeding up Functional (delay-independent) logic Simulation for synchronous digital systems. The problem needs very little new motivation-cycle-based Functional Simulation is the largest consumer of computing cycles in system design. Most existing simulators for this task can he classified as being either event driven or levelized compiled-code, with the levelized compiled code simulators generally being considered faster for this task. An alternative technique, based on evaluation using branching programs, was suggested about a decade ago in the context of switch level Functional Simulation. However, this had very limited application since it could not handle the large circuits encountered in practice. This paper resurrects the basic idea present this technique and provides significant modifications that enable its application to contemporary industrial strength circuits. We present experimental results that demonstrate up to a 10X speedup over levelized compiled code Simulation for a large suite of benchmark circuits as well as for industrial examples with over 40.000 gates.
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ICCAD - Fast Functional Simulation using branching programs
1995Co-Authors: Pranav Ashar, Sharad MalikAbstract:Abstract: This paper addresses the problem of speeding up Functional (delay-independent) logic Simulation for synchronous digital systems. The problem needs very little new motivation-cycle-based Functional Simulation is the largest consumer of computing cycles in system design. Most existing simulators for this task can he classified as being either event driven or levelized compiled-code, with the levelized compiled code simulators generally being considered faster for this task. An alternative technique, based on evaluation using branching programs, was suggested about a decade ago in the context of switch level Functional Simulation. However, this had very limited application since it could not handle the large circuits encountered in practice. This paper resurrects the basic idea present this technique and provides significant modifications that enable its application to contemporary industrial strength circuits. We present experimental results that demonstrate up to a 10X speedup over levelized compiled code Simulation for a large suite of benchmark circuits as well as for industrial examples with over 40.000 gates.
Chongmin Kyung - One of the best experts on this subject based on the ideXlab platform.
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communication efficient hardware acceleration for fast Functional Simulation
Design Automation Conference, 2004Co-Authors: Youngjin Kim, Wooseung Yang, Youngsu Kwon, Chongmin KyungAbstract:This paper presents new technology that accelerates system verification. Traditional methods for verifying Functional designs are based on logic Simulation, which becomes more time-consuming as design complexity increases. To accelerate Functional Simulation, hardware acceleration is used to offload calculation-intensive tasks from the software simulator. Hardware accelerated Simulation dramatically reduces the Simulation time. However, the communication overhead between the software simulator and hardware accelerator is becoming a new critical bottleneck. We reduce the communication overhead by exploiting burst data transfer and parallelism, which are obtained by splitting testbench and moving a part of testbench into hardware accelerator. Our experiments demonstrated that the proposed method reduces the communication overhead by a factor of about 40 compared to conventional hardware accelerated Simulation while maintaining the cycle accuracy and compatibility with the original testbench.
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DAC - Communication-efficient hardware acceleration for fast Functional Simulation
Proceedings of the 41st annual conference on Design automation - DAC '04, 2004Co-Authors: Young-il Kim, Wooseung Yang, Youngsu Kwon, Chongmin KyungAbstract:This paper presents new technology that accelerates system verification. Traditional methods for verifying Functional designs are based on logic Simulation, which becomes more time-consuming as design complexity increases. To accelerate Functional Simulation, hardware acceleration is used to offload calculation-intensive tasks from the software simulator. Hardware accelerated Simulation dramatically reduces the Simulation time. However, the communication overhead between the software simulator and hardware accelerator is becoming a new critical bottleneck. We reduce the communication overhead by exploiting burst data transfer and parallelism, which are obtained by splitting testbench and moving a part of testbench into hardware accelerator. Our experiments demonstrated that the proposed method reduces the communication overhead by a factor of about 40 compared to conventional hardware accelerated Simulation while maintaining the cycle accuracy and compatibility with the original testbench.
Zhao Xing-yun - One of the best experts on this subject based on the ideXlab platform.
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The Mathematic Model for Radar Reconnaissance Equipment Functional Simulation
Computer Simulation, 2006Co-Authors: Zhao Xing-yunAbstract:The radar reconnaissance equipment Functional Simulation is the base of the radar EW Simulation and one of developing Simulation technologies.In this paper,based on the analysis of the existing radar reconnaissance equipment mathematic models and practical application,a simple and practical radar reconnaissance equipment mathematic model is proposed from engineering view,which is mainly for modeling the functions and charac teristics of interception,measurement and recognition of the radar reconnaissance equipments.The model includes equipment noise Simulation model,measurement Simulation model,interception Simulation model and the recognition for radiant point Simulation model.It has been approved and used among the federation of radar reconnaissance equipment model based on HLA and offers a helpful reference for related design.
Srihari Cadambi - One of the best experts on this subject based on the ideXlab platform.
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a fast inexpensive and scalable hardware acceleration technique for Functional Simulation
Design Automation Conference, 2002Co-Authors: Srihari Cadambi, Chandra Mulpuri, Pranav AsharAbstract:We introduce a novel approach to accelerating Functional Simulation. The key attributes of our approach are high-performance, low-cost, scalability and low turn-around-time (TAT). We achieve speedups between 25 and 2000x over zero delay event-driven Simulation and between 75 and 1000x over cycle-based Simulation on benchmark and industrial circuits while maintaining the cost, scalability and TAT advantages of Simulation. Owing to these attributes, we believe that such an approach has potential for very wide deployment as replacement or enhancement for existing simulators. Our technology relies on a VLIW-like virtual Simulation processor (SimPLE) mapped to a single FPGA on an off-the-shelf PCI board. Primarily responsible for the speed are (i) parallelism in the processor architecture (ii) high pin count on the FPGA enabling large instruction bandwidth and (iii) high speed (124 MHz on Xilinx Virtex-II) single-FPGA implementation of the processor with regularity driven efficient place and route. Companion to the processor is the very fast SimPLE compiler which achieves compilation rates of 4 million gates/hour. In order to simulate the netlist, the compiled instructions are streamed through the FPGA, along with the Simulation vectors. This architecture plugs in naturally into any existing HDL Simulation environment. We have a working prototype based on a commercially available PCI-based FPGA board.
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DAC - A fast, inexpensive and scalable hardware acceleration technique for Functional Simulation
Proceedings of the 39th conference on Design automation - DAC '02, 2002Co-Authors: Srihari Cadambi, Chandra Mulpuri, Pranav AsharAbstract:We introduce a novel approach to accelerating Functional Simulation. The key attributes of our approach are high-performance, low-cost, scalability and low turn-around-time (TAT). We achieve speedups between 25 and 2000x over zero delay event-driven Simulation and between 75 and 1000x over cycle-based Simulation on benchmark and industrial circuits while maintaining the cost, scalability and TAT advantages of Simulation. Owing to these attributes, we believe that such an approach has potential for very wide deployment as replacement or enhancement for existing simulators. Our technology relies on a VLIW-like virtual Simulation processor (SimPLE) mapped to a single FPGA on an off-the-shelf PCI board. Primarily responsible for the speed are (i) parallelism in the processor architecture (ii) high pin count on the FPGA enabling large instruction bandwidth and (iii) high speed (124 MHz on Xilinx Virtex-II) single-FPGA implementation of the processor with regularity driven efficient place and route. Companion to the processor is the very fast SimPLE compiler which achieves compilation rates of 4 million gates/hour. In order to simulate the netlist, the compiled instructions are streamed through the FPGA, along with the Simulation vectors. This architecture plugs in naturally into any existing HDL Simulation environment. We have a working prototype based on a commercially available PCI-based FPGA board.
Stephen E. Pautler - One of the best experts on this subject based on the ideXlab platform.
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Design of Functional Simulation of renal cancer in virtual reality environments
Urology, 2005Co-Authors: Bodo E. Knudsen, Gord Campbell, Andrew Kennedy, Justin Amann, Darren Beiko, James Watterson, Ben H. Chew, John D. Denstedt, Stephen E. PautlerAbstract:Abstract Objectives The preoperative planning of partial nephrectomy can be facilitated by the ability to view the tumor and surrounding tissue in three-dimensional (3D) virtual reality (VR). A technique to convert Digital Imaging and Communications in Medicine computed tomography scan data into a fully 3D VR environment was developed. The model can be transferred to a personal computer, allowing the surgeon to view the 3D model in the operating room. Methods Computed tomography data from a patient with multifocal renal masses was converted into a 3D polygonal mesh using Amira running on a desktop personal computer with Windows XP Professional. A Silicon Graphics Monster Onyx2 running the Linux operating system was used to view the 3D stereo model in the VR environments: either the CAVE or a specialized desk called the Immersadesk. An application to view and interact with the model on a desktop personal computer was written in C++. Results A 3D model of the kidney, the multiple tumors, and the associated systems was created. The model could be viewed and manipulated in a true VR environment and on a desktop personal computer. Conclusions This project completed two major goals. First, a 3D model of a kidney containing multiple masses was created and viewed in a VR environment. Second, an interface to display the model on a desktop personal computer in the operating room was created. This is the first step in bringing VR technology to the operating room to assist the surgeon directly.
