The Experts below are selected from a list of 2757 Experts worldwide ranked by ideXlab platform
Chong-min Kyung - One of the best experts on this subject based on the ideXlab platform.
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tpartition Testbench partitioning for hardware accelerated functional verification
IEEE Design & Test of Computers, 2004Co-Authors: Young-il Kim, Chong-min KyungAbstract:This hybrid dynamic simulation scheme implements part of the simulator in software running on a processor and maps the rest onto a programmable hardware accelerator. An algorithm for hardware synthesis of behavioral Testbenches enables better partitions, resulting in lower communication costs between the two components. TPartition improves the performance of hardware accelerated simulation without a designer's remodeling effort and without losing compatibility with the original Testbench.
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communication efficient hardware acceleration for fast functional simulation
Design Automation Conference, 2004Co-Authors: Youngjin Kim, Wooseung Yang, Youngsu Kwon, Chong-min KyungAbstract:This paper presents new technology that accelerates system verification. Traditional methods for verifying functional designs are based on logic simulation, which becomes more time-consuming as design complexity increases. To accelerate functional simulation, hardware acceleration is used to offload calculation-intensive tasks from the software simulator. Hardware accelerated simulation dramatically reduces the simulation time. However, the communication overhead between the software simulator and hardware accelerator is becoming a new critical bottleneck. We reduce the communication overhead by exploiting burst data transfer and parallelism, which are obtained by splitting Testbench and moving a part of Testbench into hardware accelerator. Our experiments demonstrated that the proposed method reduces the communication overhead by a factor of about 40 compared to conventional hardware accelerated simulation while maintaining the cycle accuracy and compatibility with the original Testbench.
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Automatic translation of behavioral Testbench for fully accelerated simulation
IEEE ACM International Conference on Computer-Aided Design Digest of Technical Papers ICCAD, 2004Co-Authors: Young-il Kim, Chong-min KyungAbstract:This work presents the automated process of translating behavioral Testbench into synthesizable one for the hardware-accelerated simulation. Testbench is mainly implemented in unsynthesizable HDL description such as time delay, event control, non-static loops and sequential statements. Nonetheless, FPGA-based accelerator is limited to synthesizable design. To apply hardware acceleration to behavioral Testbench, the proposed method automatically translates Testbench into equivalent hardware by emulating the standard simulation reference model. By mapping Testbench into hardware accelerator to be merged with the design under verification, we can accelerate behavioral Testbench and remove the communication overhead between the software simulator and hardware accelerator. Our experiments demonstrated that the simulation time is reduced by a factor of about 1000 as compared to the conventional hardware accelerated simulation.
Young-il Kim - One of the best experts on this subject based on the ideXlab platform.
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tpartition Testbench partitioning for hardware accelerated functional verification
IEEE Design & Test of Computers, 2004Co-Authors: Young-il Kim, Chong-min KyungAbstract:This hybrid dynamic simulation scheme implements part of the simulator in software running on a processor and maps the rest onto a programmable hardware accelerator. An algorithm for hardware synthesis of behavioral Testbenches enables better partitions, resulting in lower communication costs between the two components. TPartition improves the performance of hardware accelerated simulation without a designer's remodeling effort and without losing compatibility with the original Testbench.
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Automatic translation of behavioral Testbench for fully accelerated simulation
IEEE ACM International Conference on Computer-Aided Design Digest of Technical Papers ICCAD, 2004Co-Authors: Young-il Kim, Chong-min KyungAbstract:This work presents the automated process of translating behavioral Testbench into synthesizable one for the hardware-accelerated simulation. Testbench is mainly implemented in unsynthesizable HDL description such as time delay, event control, non-static loops and sequential statements. Nonetheless, FPGA-based accelerator is limited to synthesizable design. To apply hardware acceleration to behavioral Testbench, the proposed method automatically translates Testbench into equivalent hardware by emulating the standard simulation reference model. By mapping Testbench into hardware accelerator to be merged with the design under verification, we can accelerate behavioral Testbench and remove the communication overhead between the software simulator and hardware accelerator. Our experiments demonstrated that the simulation time is reduced by a factor of about 1000 as compared to the conventional hardware accelerated simulation.
Wolfgang Ecker - One of the best experts on this subject based on the ideXlab platform.
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re use centric architecture for a fully accelerated Testbench environment
Design Automation Conference, 2003Co-Authors: Renate Henftling, Andreas Zinn, M Bauer, Martin Zambaldi, Wolfgang EckerAbstract:This paper presents a new technology that accelerates functional system verification. Starting with a behavioral Testbench, we developed a seamless flow to generate a re-use-oriented architecture for a synthesizable Testbench without loosing compatibility towith the original Testbench. Consequently, we combine the flexibility of a behavioral Testbench and the simulation performance of a synthesizable Testbench, while greatly reducing the modeling overhead.The approach itself is hardware independent. To prove the usability of our approach, we verified a hard disc controller on an emulator. With this setup, we achieved a speed-up factor of 5000 versus plain simulation.
Vinod Kumar - One of the best experts on this subject based on the ideXlab platform.
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Automated Coverage Register Access Technology on UVM Framework for Advanced Verification
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018Co-Authors: Gaurav Sharma, Lava Bhargava, Vinod KumarAbstract:VLSI Designs are getting more complex with the advancements in technologies. These design rules are forcing a large number of components on a single chip. The number of registers is also increasing in SOC/IP designs. The conventional verification techniques fail to provide consistent results when design consists of a large number of registers. The proposed architecture establishes a platform to automate the verification of complex intellectual properties with multiple register access. It improvises the results as compared to SystemVerilog and conventional Universal Verification Technology (UVM) Testbench. This paper focuses on advanced verification scenarios using coverage automation and Register Access Technology (RAT) on UVM verification environment. The proposed Testbench automation incorporates all necessary attributes including the functional correctness of register values. The work exposes the register database in multiple register SoC/IP design. The proposed Testbench justifies the functional coverage and fast execution of verification flow as compared to conventional verification methods.
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Self-Assertive Generic UVM Testbench for Advanced Verification of Bridge IPs
2017 14th IEEE India Council International Conference (INDICON), 2017Co-Authors: Gaurav Sharma, Lava Bhargava, Vinod KumarAbstract:This work focuses on the implementation of Universal Verification Methodology (UVM) on bridge protocols along with the conjunction of advanced verification environment. Bridge devices are helpful in joining two separate network device to establish a communication link in between them. This proposed Testbench reusable environment is capable of verifying all bridge devices and improved result as compared to System Verilog Testbench. As a case study, this paper takes ARM-Advanced High-Performance Bus (AHB) to Advanced eXtensible Interface (AXI4) Bridge v3.0 under consideration to prove the test results for bridge devices. The advanced verification Testbench incorporates the illustrations regarding C.P.U timings, simulation timings, and functional coverage to check further improvement of Design functionality. The self-checking mechanism using assertions improves the quality of UVM check by shortening time to debug and reducing time to cover for the in-depth understanding of test case output.
Graziano Pravadelli - One of the best experts on this subject based on the ideXlab platform.
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Testbench qualification of systemc tlm protocols through mutation analysis
IEEE Transactions on Computers, 2014Co-Authors: Nicola Bombieri, Franco Fummi, Valerio Guarnieri, Graziano PravadelliAbstract:Transaction-level modeling (TLM) has become the de-facto reference modeling style for system-level design and verification of embedded systems. It allows designers to implement high-level communication protocols for simulations up to $1000 \times $ faster than at register-transfer level (RTL). To guarantee interoperability between TLM IP suppliers and users, designers implement the TLM communication protocols by relying on a reference standard, such as the standard OSCI for SystemC TLM. Functional correctness of such protocols as well as their compliance to the reference TLM standard are usually verified through user-defined Testbenches, whose high quality and completeness play a key role for an efficient TLM design and verification flow. This article presents a methodology to apply mutation analysis, a technique applied in literature for SW testing, for measuring the Testbench quality in verifying TLM protocols. In particular, the methodology aims at (i) qualifying the Testbenches by considering both the TLM protocol correctness and their compliance to a defined standard (i.e., OSCI TLM), (ii) optimizing the simulation time during mutation analysis by avoiding mutation redundancies, and (iii) driving the designers in the Testbench improvement. Experimental results on benchmarks of different complexity and architectural characteristics are reported to analyze the methodology applicability.
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a Testbench specification language for systemc verification
International Conference on Hardware Software Codesign and System Synthesis, 2012Co-Authors: Giuseppe Di Guglielmo, Graziano PravadelliAbstract:Testing of embedded systems, operating in the real environment, is generally performed by using an industrial test bench that stimulates the system through sensors and human-machine interfaces. The test bench provides the engineers with a set of tools for reproducing the environmental conditions which may affect the system. On the contrary, a different approach is adopted at the early stages of the design flow, when system level languages, like SystemC, are used to describe the functionality of the design. At this level, stimuli for testing the design are traditionally generated in a random or statistical way, which makes more difficult to capture well-specific behaviors of the considered environment, thus decreasing the effectiveness and the efficiency of the verification. This is particularly evident for dynamic assertion-based verification where, to avoid vacuous passes of assertions, stimuli must reflect specific scenarios to activate the assertions.In this work, we propose a graphical framework to automatically generate stimuli, particularly suited to be used for dynamic ABV of embedded SW. The framework relies on the definition of a Testbench Specification Language (TSL) that allows to formally capture the behavior of the real environment where embedded SW is intended to be executed, i.e., how input values evolve on time intervals. Then, the framework allows to automatically synthesize TSL descriptions into SystemC-based stimuli generators, which exploit and extend the functionality of the SystemC Verification Library.
