The Experts below are selected from a list of 36819 Experts worldwide ranked by ideXlab platform
Minoru Watanabe - One of the best experts on this subject based on the ideXlab platform.
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dynamic optically reconfigurable Gate Array very large scale integration with partial reconfiguration capability
Applied Optics, 2010Co-Authors: Daisaku Seto, Mao Nakajima, Minoru WatanabeAbstract:We present a proposal of a partial reconfiguration architecture for optically reconfigurable Gate Arrays and present an 11,424 Gate dynamic optically reconfigurable Gate Array VLSI chip that was fabricated on a 96.04mm2 chip using an 0.35μm three-metal complementary metal oxide semiconductor process technology. The fabricated VLSI chip achieved a 2.21μs partial reconfiguration.
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microelectromechanical configuration of an optically reconfigurable Gate Array
IEEE Journal of Quantum Electronics, 2010Co-Authors: Hironobu Morita, Minoru WatanabeAbstract:This paper presents a proposal of a novel optically reconfigurable Gate Array architecture with a microelectromechanical system (MEMS) mirror Array that allows high-speed reconfiguration by exploiting large-bandwidth optical connections between the MEMS mirror Array and a programmable Gate Array. The MEMS mirror Array is used as a holographic memory. Four configuration contexts can be programmed electrically and dynamically onto the MEMS mirror Array as holographic memory information. The configuration procedure is executed by switching both a laser Array and an MEMS mirror Array. This experiment demonstrated a four-context 146 ns microelectromechanical configuration for a programmable Gate Array. Sub-microsecond configuration is attainable.
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programmable optically reconfigurable Gate Array architecture and its writer
Applied Optics, 2009Co-Authors: Shinya Kubota, Minoru WatanabeAbstract:Recently, optically reconfigurable Gate Arrays (ORGAs), which consist of a Gate Array VLSI, a holographic memory, and a laser Array, have been developed to achieve huge virtual Gate counts that vastly surpass those of currently available VLSIs. By exploiting the large storage capacity of a holographic memory, VLSIs with more than 1 teraGate counts will be producible. However, compared with current field programmable Gate Arrays, conventional ORGAs have one important shortcoming: they cannot be reprogrammed after fabrication. To reprogram ORGAs, a holographic memory must be disassembled from its ORGA package, then reprogrammed outside of the ORGA package using a holographic memory writer. It must then be implemented onto the ORGA package with high precision techniques beyond that which can be provided by manual assembly. Therefore, to improve this shortcoming, this paper proposes what is believed to be the world's first programmable ORGA architecture with no disassembly. Finally, the availability of this architecture is discussed based on the experimental results.
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a dynamic optically reconfigurable Gate Array perfect emulation
IEEE Journal of Quantum Electronics, 2008Co-Authors: Daisaku Seto, Minoru WatanabeAbstract:This paper presents a perfect dynamic optically reconfigurable Gate Array (DORGA) architecture emulation using a holographic memory and a conventional ORGA-VLSI. In ORGAs, although a large virtual Gate count can be realized by exploiting the large-capacity storage capability of a holographic memory, the actual Gate count, which is the Gate count of a programmable Gate Array VLSI, is important to increase the instantaneous performance. Nevertheless, in previously proposed ORGA-VLSIs, the static configuration memory to store a single configuration context consumed a large implementation area of the ORGA-VLSIs and prevented the realization of large-Gate-count ORGA-VLSIs. Therefore, a DORGA architecture has been proposed in order to increase the Gate density. It uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. However, to date, demonstration of a perfect optically reconfigurable architecture for DORGA-VLSIs has never been presented. Therefore, in this study, the DORGA architecture was perfectly emulated, and the performance, particularly the reconfiguration context retention time, was measured experimentally. The advantages of this architecture are discussed in relation to the results.
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dynamic optically reconfigurable Gate Array
Japanese Journal of Applied Physics, 2006Co-Authors: Minoru Watanabe, Fuminori KobayashiAbstract:Optically reconfigurable Gate Arrays (ORGAs) can readily enable both fast reconfiguration and numerous reconfiguration contexts using an optical holographic memory and optical wide-band reconfiguration connections. Such devices present the possibility of large virtual Gate-count very large scale integrations (VLSIs). However, the real Gate-count of the VLSI part of the devices is too small–only 80. Moreover, the reconfiguration speed is not sufficiently fast: 16 to 20 µs. For those reasons, this paper clarifies the architecture issues and presents a new architecture of a dynamic optically reconfigurable Gate Array (DORGA) to improve them. In addition, a comparison is made of results obtained using the previously proposed devices and DORGAs under the same environment. Finally, this paper presents a new design of a 51,272-Gate-count DORGA with the new architecture.
Hiroshi Nakamura - One of the best experts on this subject based on the ideXlab platform.
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a double level v sub th select Gate Array architecture for multilevel nand flash memories
IEEE Journal of Solid-state Circuits, 1996Co-Authors: Ken Takeuchi, Tomoharu Tanaka, Hiroshi NakamuraAbstract:In multilevel flash memories, the threshold voltages of the memory cells should be controlled precisely. This paper describes how in a conventional NAND flash memory, the threshold voltages of the memory cells fluctuate due to Array noise during the bit-by-bit program verify operation, and as a result, the threshold voltage distribution becomes wider. This paper describes a new Array architecture, "A double-level-V/sub th/ select Gate Array architecture" to eliminate the Array noise, together with a reduction of the cell area. The Array noise is mainly caused by interbitline capacitive coupling noise and by the high resistance of the diffused source-line. The threshold voltage fluctuation can be as much as 0.7 V in a conventional Array. In the proposed Array, bitlines are alternately selected, and the unselected bitlines are used as low resistance source-lines. Moreover, the unselected bitlines form a shield between the neighboring selected bitlines. As a result, the Array noise is strongly suppressed. The threshold voltage fluctuation is estimated to be as small as 0.03 V in the proposed Array and a reliable operation of a multilevel NAND flash memory can be realized.
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a double level v sub th select Gate Array architecture for multi level nand flash memories
Symposium on VLSI Circuits, 1995Co-Authors: Ken Takeuchi, Tomoharu Tanaka, Hiroshi NakamuraAbstract:This paper first explains that Gate Array noise during a bit-by-bit program verify operation, named source line noise, is estimated to have a crucial adverse effect on the threshold voltage (V/sub th/) control and causes a serious problem in Multi-Level NAND Flash Memories. Then a new Array architecture, a Double-Level-V/sub th/ Select Gate Array Architecture, is introduced to eliminate this noise without cell area penalty.
Ken Takeuchi - One of the best experts on this subject based on the ideXlab platform.
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a double level v sub th select Gate Array architecture for multilevel nand flash memories
IEEE Journal of Solid-state Circuits, 1996Co-Authors: Ken Takeuchi, Tomoharu Tanaka, Hiroshi NakamuraAbstract:In multilevel flash memories, the threshold voltages of the memory cells should be controlled precisely. This paper describes how in a conventional NAND flash memory, the threshold voltages of the memory cells fluctuate due to Array noise during the bit-by-bit program verify operation, and as a result, the threshold voltage distribution becomes wider. This paper describes a new Array architecture, "A double-level-V/sub th/ select Gate Array architecture" to eliminate the Array noise, together with a reduction of the cell area. The Array noise is mainly caused by interbitline capacitive coupling noise and by the high resistance of the diffused source-line. The threshold voltage fluctuation can be as much as 0.7 V in a conventional Array. In the proposed Array, bitlines are alternately selected, and the unselected bitlines are used as low resistance source-lines. Moreover, the unselected bitlines form a shield between the neighboring selected bitlines. As a result, the Array noise is strongly suppressed. The threshold voltage fluctuation is estimated to be as small as 0.03 V in the proposed Array and a reliable operation of a multilevel NAND flash memory can be realized.
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a double level v sub th select Gate Array architecture for multi level nand flash memories
Symposium on VLSI Circuits, 1995Co-Authors: Ken Takeuchi, Tomoharu Tanaka, Hiroshi NakamuraAbstract:This paper first explains that Gate Array noise during a bit-by-bit program verify operation, named source line noise, is estimated to have a crucial adverse effect on the threshold voltage (V/sub th/) control and causes a serious problem in Multi-Level NAND Flash Memories. Then a new Array architecture, a Double-Level-V/sub th/ Select Gate Array Architecture, is introduced to eliminate this noise without cell area penalty.
Daisaku Seto - One of the best experts on this subject based on the ideXlab platform.
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dynamic optically reconfigurable Gate Array very large scale integration with partial reconfiguration capability
Applied Optics, 2010Co-Authors: Daisaku Seto, Mao Nakajima, Minoru WatanabeAbstract:We present a proposal of a partial reconfiguration architecture for optically reconfigurable Gate Arrays and present an 11,424 Gate dynamic optically reconfigurable Gate Array VLSI chip that was fabricated on a 96.04mm2 chip using an 0.35μm three-metal complementary metal oxide semiconductor process technology. The fabricated VLSI chip achieved a 2.21μs partial reconfiguration.
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a dynamic optically reconfigurable Gate Array perfect emulation
IEEE Journal of Quantum Electronics, 2008Co-Authors: Daisaku Seto, Minoru WatanabeAbstract:This paper presents a perfect dynamic optically reconfigurable Gate Array (DORGA) architecture emulation using a holographic memory and a conventional ORGA-VLSI. In ORGAs, although a large virtual Gate count can be realized by exploiting the large-capacity storage capability of a holographic memory, the actual Gate count, which is the Gate count of a programmable Gate Array VLSI, is important to increase the instantaneous performance. Nevertheless, in previously proposed ORGA-VLSIs, the static configuration memory to store a single configuration context consumed a large implementation area of the ORGA-VLSIs and prevented the realization of large-Gate-count ORGA-VLSIs. Therefore, a DORGA architecture has been proposed in order to increase the Gate density. It uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. However, to date, demonstration of a perfect optically reconfigurable architecture for DORGA-VLSIs has never been presented. Therefore, in this study, the DORGA architecture was perfectly emulated, and the performance, particularly the reconfiguration context retention time, was measured experimentally. The advantages of this architecture are discussed in relation to the results.
Tomoharu Tanaka - One of the best experts on this subject based on the ideXlab platform.
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a double level v sub th select Gate Array architecture for multilevel nand flash memories
IEEE Journal of Solid-state Circuits, 1996Co-Authors: Ken Takeuchi, Tomoharu Tanaka, Hiroshi NakamuraAbstract:In multilevel flash memories, the threshold voltages of the memory cells should be controlled precisely. This paper describes how in a conventional NAND flash memory, the threshold voltages of the memory cells fluctuate due to Array noise during the bit-by-bit program verify operation, and as a result, the threshold voltage distribution becomes wider. This paper describes a new Array architecture, "A double-level-V/sub th/ select Gate Array architecture" to eliminate the Array noise, together with a reduction of the cell area. The Array noise is mainly caused by interbitline capacitive coupling noise and by the high resistance of the diffused source-line. The threshold voltage fluctuation can be as much as 0.7 V in a conventional Array. In the proposed Array, bitlines are alternately selected, and the unselected bitlines are used as low resistance source-lines. Moreover, the unselected bitlines form a shield between the neighboring selected bitlines. As a result, the Array noise is strongly suppressed. The threshold voltage fluctuation is estimated to be as small as 0.03 V in the proposed Array and a reliable operation of a multilevel NAND flash memory can be realized.
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a double level v sub th select Gate Array architecture for multi level nand flash memories
Symposium on VLSI Circuits, 1995Co-Authors: Ken Takeuchi, Tomoharu Tanaka, Hiroshi NakamuraAbstract:This paper first explains that Gate Array noise during a bit-by-bit program verify operation, named source line noise, is estimated to have a crucial adverse effect on the threshold voltage (V/sub th/) control and causes a serious problem in Multi-Level NAND Flash Memories. Then a new Array architecture, a Double-Level-V/sub th/ Select Gate Array Architecture, is introduced to eliminate this noise without cell area penalty.
