The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
Jin Jang - One of the best experts on this subject based on the ideXlab platform.
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effect of top Gate Bias on photocurrent and negative Bias illumination stress instability in dual Gate amorphous indium gallium zinc oxide thin film transistor
Applied Physics Letters, 2015Co-Authors: Eunji Lee, Delwar Hossain Chowdhury, Min Sang Park, Jin JangAbstract:We have studied the effect of top Gate Bias (VTG) on the generation of photocurrent and the decay of photocurrent for back channel etched inverted staggered dual Gate structure amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film-transistors. Upon 5 min of exposure of 365 nm wavelength and 0.7 mW/cm2 intensity light with negative bottom Gate Bias, the maximum photocurrent increases from 3.29 to 322 pA with increasing the VTG from −15 to +15 V. By changing VTG from negative to positive, the Fermi level (EF) shifts toward conduction band edge (EC), which substantially controls the conversion of neutral vacancy to charged one (VO → VO+/VO2+ + e−/2e−), peroxide (O22−) formation or conversion of ionized interstitial (Oi2−) to neutral interstitial (Oi), thus electron concentration at conduction band. With increasing the exposure time, more carriers are generated, and thus, maximum photocurrent increases until being saturated. After negative Bias illumination stress, the transfer curve shows −2.7 V shift at VTG = −15 V, which gradually decreases to −0.42 V shift at VTG = +15 V. It clearly reveals that the position of electron quasi-Fermi level controls the formation of donor defects (VO+/VO2+/O22−/Oi) and/or hole trapping in the a-IGZO /interfaces.
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Gate Bias stress induced hump effect in transfer characteristics of amorphous indium galium zinc oxide thin fim transistors with various channel widths
Applied Physics Letters, 2011Co-Authors: Mallory Mativenga, Man Ju Seok, Jin JangAbstract:A hump in the subthreshold regime of the transfer characteristics is reported for amorphous-indium-galium-zinc-oxide thin-film transistors (TFTs) when they are exposed to large positive Gate Bias-stress. As stress time progresses, transfer characteristics shift in two opposite directions; the main transistor shifts in the positive, while the hump shifts in the negative Gate-voltage direction. The hump occurs at the same current level in all TFTs with channel widths ranging from 10 to 200 μm, which supports the exclusion of bulk and back surface effects. We therefore propose the accumulation of positive charge at the interface of the channel edges, along the channel width direction, as the origin of the hump effect.
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A full-swing a-IGZO TFT-based inverter with a top-Gate-Bias-induced depletion load
IEEE Electron Device Letters, 2011Co-Authors: Man Ju Seok, Deok Yeol Kim, Min Hyuk Choi, Mallory Mativenga, Di Geng, Jin JangAbstract:A high-performance inverter implemented with single-Gated driving and dual-Gated load amorphous-indium–gallium–zinc–oxide thin-film transistors (TFTs) is demonstrated. The threshold voltage of the load TFT shifts to the negative Gate voltage direction when a constant positive Bias is applied on the top Gate while sweeping the bottom Gate. Using a positive top Gate Bias, the load TFT can be operated in the depletion mode to realize inverters with excellent switching characteristics, such as a wider swing range and a higher noise margin.
Ting-chang Chang - One of the best experts on this subject based on the ideXlab platform.
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investigation of on current degradation behavior induced by surface hydrolysis effect under negative Gate Bias stress in amorphous ingazno thin film transistors
Applied Physics Letters, 2014Co-Authors: Ting-chang Chang, Kuanchang Chang, Tsungming Tsai, Tienyu Hsieh, Min Chen Chen, Wuching ChouAbstract:This study investiGates the electrical instability under negative Gate Bias stress (NGBS) induced by surface hydrolysis effect. Electrical characteristics exhibit instability for amorphous InGaZnO (a-IGZO) Thin Film Transistors (TFTs) under NGBS, in which on-current degradation and current crowding phenomenon can be observed. When the negative Gate Bias is applied on the TFT, hydrogen ions will dissociate from ZnO-H bonds and the dissociated hydrogen ions will cause electrical instability under NGBS. The ISE-Technology Computer Aided Design simulation tool and moisture partial pressure modulation measurement are utilized to clarify the anomalous degradation behavior.
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investigation of the Gate Bias induced instability for ingazno tfts under dark and light illumination
Thin Solid Films, 2011Co-Authors: Techih Chen, Ting-chang Chang, Shih Ching Chen, Tienyu Hsieh, Chengda Tsai, Chia Sheng Lin, Fuyen Jian, Mingyen TsaiAbstract:Abstract Mechanism of the instability for indium–gallium–zinc oxide thin film transistors caused by Gate-Bias stress performed in the dark and light illumination was investiGated in this paper. The parallel Vt shift with no degradation of subthreshold swing (S.S) and the fine fitting to the stretched-exponential equation indicate that charge trapping model dominates the degradation behavior under positive Gate-Bias stress. In addition, the significant Gate-Bias dependence of Vt shift demonstrates that electron trapping effect easily occurs under large Gate-Bias since the average effective energy barrier of electron injection decreases with increasing Gate Bias. Moreover, the noticeable decrease of threshold voltage (Vt) shift under illuminated positive Gate-Bias stress and the accelerated recovery rate in the light indicate that the charge detrapping mechanism occurs under light illumination. Finally, the apparent negative Vt shift under illuminated negative Gate-Bias stress was investiGated in this paper. The average effectively energy barrier of electron and hole injection were extracted to clarify that the serious Vt degradation behavior comparing with positive Gate-Bias stress was attributed to the lower energy barrier for hole injection.
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investigating the degradation behavior caused by charge trapping effect under dc and ac Gate Bias stress for ingazno thin film transistor
Applied Physics Letters, 2011Co-Authors: Techih Chen, Ting-chang Chang, Tienyu Hsieh, Fuyen Jian, Chihtsung Tsai, Shengyao Huang, Chia Sheng LinAbstract:This letter investiGates the degradation mechanism of amorphous indium-gallium-zinc oxide thin-film transistors under Gate-Bias stress. The larger Vt shift under positive AC Gate-Bias stress when compared to DC operation indicates that an extra electron trapping mechanism occurs during rising/falling time during the AC pulse period. In contrast, the degradation behavior under illuminated negative Gate-Bias stress exhibits the opposite degradation tendency. Since electron and hole trapping are the dominant degradation mechanisms under positive and illuminated negative Gate-Bias stress, respectively, the different degradation tendencies under AC/DC operation can be attributed to the different trapping efficiency of electrons and holes.
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behaviors of ingazno thin film transistor under illuminated positive Gate Bias stress
Applied Physics Letters, 2010Co-Authors: Techih Chen, Ting-chang Chang, Shih Ching Chen, Tienyu Hsieh, Chia Sheng Lin, Chihtsung Tsai, Mingchin Hung, Jiunjye Chang, Polun ChenAbstract:In this letter, we investiGate the impact of the light illumination on the stability of indium–gallium– zinc oxide thin film transistors under positive Gate-Bias stress. The noticeable decrease in threshold voltage Vt shift more than 5.5 V under illuminated positive Gate-Bias stress indicates a superior reliability in contrast with the dark stress. The accelerated Vt recovery characteristic compared with dark recovery demonstrates that the charge detrapping effect was enhanced under illumination. Furthermore, the average effective energy barrier of charge trapping and detrapping was derived to verify that illumination can excite the trapped charges and accelerate the charge detrapping process. © 2010 American Institute of Physics. doi:10.1063/1.3481676
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Bias-induced oxygen adsorption in zinc tin oxide thin film transistors under dynamic stress
Applied Physics Letters, 2010Co-Authors: Yu-chun Chen, Ting-chang Chang, Shih Ching Chen, Wan Fang Chung, Ya-hsiang Tai, Tseung-yuen TsengAbstract:This study investiGates the effects of Bias-induced oxygen adsorption on the electrical characteristic instability of zinc tin oxide thin film transistors in different ambient oxygen partial pressures. When oxygen pressure is largest, the threshold voltages showed the quickest increase but the slowest recovery during the stress phase and recovery phase, respectively. This finding corresponds to the charge trapping time constant and recovery time constant, which are extracted by fitting the stretched-exponential equation and which exhibit a relationship with oxygen pressure. We suggest that the Gate Bias reduces the activation energy of oxygen adsorption during Gate Bias stress.
Takhee Lee - One of the best experts on this subject based on the ideXlab platform.
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Gate Bias stress dependent photoconductive characteristics of multi layer mos2 field effect transistors
Nanotechnology, 2014Co-Authors: Kyungjune Cho, Taeyoung Kim, Woanseo Park, Juhun Park, Dongku Kim, Jingon Jang, Hyunhak Jeong, Seunghun Hong, Takhee LeeAbstract:We investiGated the photoconductive characteristics of molybdenum disulfide (MoS2) field-effect transistors (FETs) that were fabricated with mechanically exfoliated multi-layer MoS2 flakes. Upon exposure to UV light, we observed an increase in the MoS2 FET current because of electron-hole pair generation. The MoS2 FET current decayed after the UV light was turned off. The current decay processes were fitted using exponential functions with different decay characteristics. Specifically, a fast decay was used at the early stages immediately after turning off the light to account for the exciton relaxation, and a slow decay was used at later stages long after turning off the light due to charge trapping at the oxygen-related defect sites on the MoS2 surface. This photocurrent decay phenomenon of the MoS2 FET was influenced by the measurement environment (i.e., vacuum or oxygen environment) and the electrical Gate-Bias stress conditions (positive or negative Gate Biases). The results of this study will enhance the understanding of the influence of environmental and measurement conditions on the optical and electrical properties of MoS2 FETs.
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electric stress induced threshold voltage instability of multilayer mos2 field effect transistors
ACS Nano, 2013Co-Authors: Kyungjune Cho, Woongki Hong, Taeyoung Kim, Woanseo Park, Juhun Park, Jingon Jang, Hyunhak Jeong, Seunghun Hong, Takhee LeeAbstract:We investiGated the Gate Bias stress effects of multilayered MoS2 field effect transistors (FETs) with a back-Gated configuration. The electrical stability of the MoS2 FETs can be significantly influenced by the electrical stress type, relative sweep rate, and stress time in an ambient environment. Specifically, when a positive Gate Bias stress was applied to the MoS2 FET, the current of the device decreased and its threshold shifted in the positive Gate Bias direction. In contrast, with a negative Gate Bias stress, the current of the device increased and the threshold shifted in the negative Gate Bias direction. The Gate Bias stress effects were enhanced when a Gate Bias was applied for a longer time or when a slower sweep rate was used. These phenomena can be explained by the charge trapping due to the adsorption or desorption of oxygen and/or water on the MoS2 surface with a positive or negative Gate Bias, respectively, under an ambient environment. This study will be helpful in understanding the elect...
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investigation of threshold voltage instability induced by Gate Bias stress in zno nanowire field effect transistors
Nanotechnology, 2012Co-Authors: Minhyeok Choe, Woojin Park, Jang Won Kang, Sehee Jeong, Woongki Hong, Byoung Hun Lee, Seongju Park, Takhee LeeAbstract:We investiGated the threshold voltage instability induced by Gate Bias (VG) stress in ZnO nanowire (NW) field effect transistors (FETs). By increasing the VG sweep ranges and repeatedly measuring the electrical characteristics of the ZnO NW FETs, the VG stress was produced in the dielectric layer underneath the ZnO NW. Consequently, the electrical conductance of the ZnO NW FETs decreased, and the threshold voltage shifted towards the positive VG direction. This threshold voltage instability induced by the VG stress is associated with the trapping of charges in the interface trap sites located in the ZnO NW–dielectric interface. Our study will be helpful for understanding the stability of ZnO NW FETs during repetitive operations.
Tseung-yuen Tseng - One of the best experts on this subject based on the ideXlab platform.
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Bias-induced oxygen adsorption in zinc tin oxide thin film transistors under dynamic stress
Applied Physics Letters, 2010Co-Authors: Yu-chun Chen, Ting-chang Chang, Shih Ching Chen, Wan Fang Chung, Ya-hsiang Tai, Tseung-yuen TsengAbstract:This study investiGates the effects of Bias-induced oxygen adsorption on the electrical characteristic instability of zinc tin oxide thin film transistors in different ambient oxygen partial pressures. When oxygen pressure is largest, the threshold voltages showed the quickest increase but the slowest recovery during the stress phase and recovery phase, respectively. This finding corresponds to the charge trapping time constant and recovery time constant, which are extracted by fitting the stretched-exponential equation and which exhibit a relationship with oxygen pressure. We suggest that the Gate Bias reduces the activation energy of oxygen adsorption during Gate Bias stress.
Elvira Fortunato - One of the best experts on this subject based on the ideXlab platform.
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environmental optical and electrical stability study of solution processed zinc tin oxide thin film transistors
IEEE\ OSA Journal of Display Technology, 2011Co-Authors: Pradipta K Nayak, J V Pinto, G Goncalves, Rodrigo Martins, Elvira FortunatoAbstract:In this paper, we report the environmental, optical, and Gate Bias stress stability of amorphous zinc-tin-oxide (ZTO) thin-film transistors (TFTs) fabricated by sol-gel spin-coating method. The ZTO TFTs showed excellent environmental and optical stability. The threshold voltage stability of ZTO TFTs was sensitive to both positive and negative Gate Bias stress. Maximum threshold voltage shifting of +1.9 and -3.2 V was observed under a Gate Bias stress of +10 and -10 V, respectively, with no significant change to subthreshold swing value.