The Experts below are selected from a list of 168 Experts worldwide ranked by ideXlab platform
I-chun Cheng - One of the best experts on this subject based on the ideXlab platform.
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Mobility Enhancement in RF-Sputtered MgZnO/ZnO Heterostructure Thin-Film Transistors
IEEE Transactions on Electron Devices, 2016Co-Authors: Bo-shiung Wang, Yun-shiuan Li, I-chun ChengAbstract:Coplanar top-gate MgZnO/ZnO heterostructure thin-film transistors (TFTs) are fabricated on glass substrates using a large-area processing compatible RF-sputtering technique. The field-effect mobility increases with the Mg content in the MgZnO capping layer. The threshold voltage, saturation field-effect mobility, and ON/OFF current ratio of an Mg0.2Zn0.8O/ZnO heterostructure TFT are -0.55 V, 84.22 cm2 V-1 s-1, and 3 × 106, respectively. In comparison with a ZnO TFT, the mobility is enhanced by a factor of >50. Inverters based on Mg0.2Zn0.8O/ZnO TFTs are then demonstrated by connecting load transistors operated at VGS = VDD (supply voltage) to drive transistors. A peak gain magnitude of 19.6 is obtained in the Mg0.2Zn0.8O/ZnO inverter with a Geometric Aspect ratio of 15 at VDD of 18 V.
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Flexible Complementary Oxide–Semiconductor-Based Circuits Employing n-Channel ZnO and p-Channel SnO Thin-Film Transistors
IEEE Electron Device Letters, 2016Co-Authors: Yun-shiuan Li, Jyun-ci He, Dung-yue Su, Feng-yu Tsai, I-chun ChengAbstract:In this letter, we report flexible fully oxide-based complementary metal-oxide-semiconductor (CMOS) inverters and ring oscillators by the monolithic integration of flexible n-channel zinc oxide (ZnO) and p-channel tin monoxide (SnO) thin-film transistors (TFTs). Inverted-staggered bottom-gated TFTs were fabricated by a low-temperature RF-sputtering technique. The static voltage gain of a flexible oxide-TFT-based CMOS inverter with a Geometric Aspect ratio of 5 is ~12 at a supplied voltage (VDD) of 12 V. An oscillation frequency of ~18.4 kHz is obtained from a five-stage flexible oxide-TFT-based CMOS voltage control ring oscillator at VDD of 12 V. Degradations of TFTs, inverters, and ring oscillators have been observed when a mechanical tensile strain is applied, whereas the influence of compressive strain is negligible.
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Complementary Oxide–Semiconductor-Based Circuits With n-Channel ZnO and p-Channel SnO Thin-Film Transistors
IEEE Electron Device Letters, 2014Co-Authors: I-chung Chiu, Yun-shiuan Li, Min-sheng Tu, I-chun ChengAbstract:Fully oxide thin-film transistor (TFT)-based complementary metal-oxide-semiconductor (CMOS) ring oscillators are reported, for the first time, using large-area-compatible sputtering processes. The p-channel tin monoxide (SnO) and n-channel zinc oxide (ZnO) TFTs used in the CMOS inverter have inverted-staggered bottom-gate structures. The SnO TFT exhibits a threshold voltage (Vth) of 3.5 V, field-effect mobility of 0.33 cm2/V-s, subthreshold swing of 2.5 V/decade, and ON/OFF current ratio of ~103. The corresponding values for the ZnO TFT are 6.22 V, 3.5 cm2/V-s, 350 mV/decade, and >106. The achieved voltage gain of the CMOS inverters is ~17 at a supplied voltage (VDD) of 10 V when the Geometric Aspect ratio is 5. An oscillation frequency of 2 kHz is obtained from a five-stage oxide-based CMOS voltage control oscillator at (VDD) of 14 V.
Yun-shiuan Li - One of the best experts on this subject based on the ideXlab platform.
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Mobility Enhancement in RF-Sputtered MgZnO/ZnO Heterostructure Thin-Film Transistors
IEEE Transactions on Electron Devices, 2016Co-Authors: Bo-shiung Wang, Yun-shiuan Li, I-chun ChengAbstract:Coplanar top-gate MgZnO/ZnO heterostructure thin-film transistors (TFTs) are fabricated on glass substrates using a large-area processing compatible RF-sputtering technique. The field-effect mobility increases with the Mg content in the MgZnO capping layer. The threshold voltage, saturation field-effect mobility, and ON/OFF current ratio of an Mg0.2Zn0.8O/ZnO heterostructure TFT are -0.55 V, 84.22 cm2 V-1 s-1, and 3 × 106, respectively. In comparison with a ZnO TFT, the mobility is enhanced by a factor of >50. Inverters based on Mg0.2Zn0.8O/ZnO TFTs are then demonstrated by connecting load transistors operated at VGS = VDD (supply voltage) to drive transistors. A peak gain magnitude of 19.6 is obtained in the Mg0.2Zn0.8O/ZnO inverter with a Geometric Aspect ratio of 15 at VDD of 18 V.
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Flexible Complementary Oxide–Semiconductor-Based Circuits Employing n-Channel ZnO and p-Channel SnO Thin-Film Transistors
IEEE Electron Device Letters, 2016Co-Authors: Yun-shiuan Li, Jyun-ci He, Dung-yue Su, Feng-yu Tsai, I-chun ChengAbstract:In this letter, we report flexible fully oxide-based complementary metal-oxide-semiconductor (CMOS) inverters and ring oscillators by the monolithic integration of flexible n-channel zinc oxide (ZnO) and p-channel tin monoxide (SnO) thin-film transistors (TFTs). Inverted-staggered bottom-gated TFTs were fabricated by a low-temperature RF-sputtering technique. The static voltage gain of a flexible oxide-TFT-based CMOS inverter with a Geometric Aspect ratio of 5 is ~12 at a supplied voltage (VDD) of 12 V. An oscillation frequency of ~18.4 kHz is obtained from a five-stage flexible oxide-TFT-based CMOS voltage control ring oscillator at VDD of 12 V. Degradations of TFTs, inverters, and ring oscillators have been observed when a mechanical tensile strain is applied, whereas the influence of compressive strain is negligible.
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Complementary Oxide–Semiconductor-Based Circuits With n-Channel ZnO and p-Channel SnO Thin-Film Transistors
IEEE Electron Device Letters, 2014Co-Authors: I-chung Chiu, Yun-shiuan Li, Min-sheng Tu, I-chun ChengAbstract:Fully oxide thin-film transistor (TFT)-based complementary metal-oxide-semiconductor (CMOS) ring oscillators are reported, for the first time, using large-area-compatible sputtering processes. The p-channel tin monoxide (SnO) and n-channel zinc oxide (ZnO) TFTs used in the CMOS inverter have inverted-staggered bottom-gate structures. The SnO TFT exhibits a threshold voltage (Vth) of 3.5 V, field-effect mobility of 0.33 cm2/V-s, subthreshold swing of 2.5 V/decade, and ON/OFF current ratio of ~103. The corresponding values for the ZnO TFT are 6.22 V, 3.5 cm2/V-s, 350 mV/decade, and >106. The achieved voltage gain of the CMOS inverters is ~17 at a supplied voltage (VDD) of 10 V when the Geometric Aspect ratio is 5. An oscillation frequency of 2 kHz is obtained from a five-stage oxide-based CMOS voltage control oscillator at (VDD) of 14 V.
F. C. Castaldo - One of the best experts on this subject based on the ideXlab platform.
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Transversal Noise Current: An Excess Noise in CMOS Split-Drain Transistors
IEEE Transactions on Electron Devices, 2007Co-Authors: F. C. Castaldo, C. Dos Reis A. FilhoAbstract:An excess-noise current in CMOS magnetic sensitive field effect transistor (MAGFET) split-drain transistors is investigated, and a new noise model is proposed. The model is based on the existence of the transversal noise current that stems from the inversion charge layer in the MOS transistor channel. This excess-noise current, along with the one predicted by the classical MOS transistor, produces the total split-drain noise current. Noise spectral density measurements were carried out to verify the proposed model for split-drain MAGFETs manufactured in 0.8 and 0.35 mum CMOS, with an equal Geometric Aspect ratio of 10mum/10mum
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Transversal noise current in split-drain transistors
2006 IEEE International Symposium on Circuits and Systems, 2006Co-Authors: F. C. Castaldo, C.a. Reis FilhoAbstract:An excess noise current in CMOS MAGFET split drain transistor is investigated and a new noise model is proposed. It is based on the existence of the transversal noise current that stems from the inversion charge from the MOS transistor channel. This noise current along with the one predicted by the classical MOS transistor produces the total split-drain noise current. This noise current impacts the signal-to-noise ratio and minimum detectable magnetic field, parameters of interest in CMOS-based magnetic sensors. Noise measurement were applied to verify the combined effect of this noise currents. Essentially, it has been observed that a negative correlation between drain currents takes place in split-drain transistor operating in saturation region. Noise voltage power spectral density (Voltage-PSD) measurements were made for split-drain MAGFETs manufactured in 0.8mum, 0.6mum and 0.35mum CMOS with Geometric Aspect ratio of 10mum/10mum, 24mum/30mum and 10mum/10mum, respectively
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Bias dependence of noise correlation in MAGFETs
16th Symposium on Integrated Circuits and Systems Design 2003. SBCCI 2003. Proceedings., 2003Co-Authors: F. C. Castaldo, J.p.c. Cajueiro, C.a. Dos ReisAbstract:In this paper, measurement results of noise power spectral density in p-channel split-drain MAGFETs operating under various levels of bias current are presented and discussed. It has been observed that correlation increases for decreasing levels of bias current. For currents below 5 /spl mu/A, noise correlation is higher than 50%, rising rapidly towards total correlation. These results indicate that this type of magnetic sensor can be used for low level detection, contradicting what has been so far mentioned in the literature. Measurements were made for bias current ranging from 2 /spl mu/A to circa 70 /spl mu/A using MAGFETs manufactured in 0.8 /spl mu/m CMOS with Geometric Aspect ratios of 10 /spl mu/m/10 /spl mu/m, 24 /spl mu/m/24 /spl mu/m and 24 /spl mu/m/30 /spl mu/m.
C.a. Reis Filho - One of the best experts on this subject based on the ideXlab platform.
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Transversal noise current in split-drain transistors
2006 IEEE International Symposium on Circuits and Systems, 2006Co-Authors: F. C. Castaldo, C.a. Reis FilhoAbstract:An excess noise current in CMOS MAGFET split drain transistor is investigated and a new noise model is proposed. It is based on the existence of the transversal noise current that stems from the inversion charge from the MOS transistor channel. This noise current along with the one predicted by the classical MOS transistor produces the total split-drain noise current. This noise current impacts the signal-to-noise ratio and minimum detectable magnetic field, parameters of interest in CMOS-based magnetic sensors. Noise measurement were applied to verify the combined effect of this noise currents. Essentially, it has been observed that a negative correlation between drain currents takes place in split-drain transistor operating in saturation region. Noise voltage power spectral density (Voltage-PSD) measurements were made for split-drain MAGFETs manufactured in 0.8mum, 0.6mum and 0.35mum CMOS with Geometric Aspect ratio of 10mum/10mum, 24mum/30mum and 10mum/10mum, respectively
C. Dos Reis A. Filho - One of the best experts on this subject based on the ideXlab platform.
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Transversal Noise Current: An Excess Noise in CMOS Split-Drain Transistors
IEEE Transactions on Electron Devices, 2007Co-Authors: F. C. Castaldo, C. Dos Reis A. FilhoAbstract:An excess-noise current in CMOS magnetic sensitive field effect transistor (MAGFET) split-drain transistors is investigated, and a new noise model is proposed. The model is based on the existence of the transversal noise current that stems from the inversion charge layer in the MOS transistor channel. This excess-noise current, along with the one predicted by the classical MOS transistor, produces the total split-drain noise current. Noise spectral density measurements were carried out to verify the proposed model for split-drain MAGFETs manufactured in 0.8 and 0.35 mum CMOS, with an equal Geometric Aspect ratio of 10mum/10mum
