The Experts below are selected from a list of 207 Experts worldwide ranked by ideXlab platform

Liu Shubin - One of the best experts on this subject based on the ideXlab platform.

  • A Design of FPGA Based Small Animal PET Real Time Digital Signal Processing and Correction Logic
    arXiv: Signal Processing, 2018
    Co-Authors: Lei Zhao, Kairen Chen, Peipei Deng, Liu Shubin
    Abstract:

    Small animal Positron Emission Tomography (PET) is dedicated to small animal imaging. Animals used in experiments, such as rats and monkeys, are often much smaller than human bodies, which requires higher position and energy precision of the PET imaging system. Besides, Flexibility, high efficiency are also the major demands of a practical PET system. These requires a high-quality analog front-end and a digital signal processing logic with high efficiency and compatibility of multiple data processing modes. The digital signal processing logic of the small animal PET system presented in this paper implements 32-channel signal processing in a single Xilinx Artix-7 family of Field-Programmable Gate Array (FPGA). The logic is designed to support three online modes which are regular package mode, flood map and energy spectrum histogram. Several functions are integrated, including two-dimensional (2D) raw position calculation, crystal identification, events filtering, etc. Besides, a series of online corrections are also integrated, such as photon peak correction to 511 keV and timing offset correction with crystal granularity. A Gigabit Ethernet Interface is utilized for data transfer, Look-Up Tables (LUTs) configuration and commands issuing. The pipe-line logic processes the signals at 125 MHz with a rate of 1,000,000 events/s. A series of initial tests are conducted. The results indicate that the digital processing logic achieves the expectations.

Ghaïs El Zein - One of the best experts on this subject based on the ideXlab platform.

  • VTC Spring - 60 GHz High Data Rate Wireless Communication System
    VTC Spring 2009 - IEEE 69th Vehicular Technology Conference, 2009
    Co-Authors: Lahatra Rakotondrainibe, Yvan Kokar, Gheorghe Zaharia, Ghaïs El Zein
    Abstract:

    This paper presents the design and the realization of a 60 GHz wireless Gigabit Ethernet communication system. A differential encoded binary phase shift keying modulation (DBPSK) and differential demodulation schemes are adopted for the IF blocks. The Gigabit Ethernet Interface allows a high speed transfer of multimedia files via a 60 GHz wireless link. First measurement results are shown for 875 Mbps data rate.

Lei Zhao - One of the best experts on this subject based on the ideXlab platform.

  • Real-Time FPGA-based Digital Signal Processing and Correction for a Small Animal PET
    IEEE Transactions on Nuclear Science, 2019
    Co-Authors: Lei Zhao, Kairen Chen, Peipei Deng, Shubin Liu
    Abstract:

    Small animal Positron Emission Tomography (PET) is dedicated to small animal imaging, which requires high position and energy precision, as well as good flexibility and efficiency of the electronics. This paper presents the design of a digital signal processing logic for a marmoset brain PET system based on LYSO crystal arrays, SiPMs, and the resistive network readout method. We implement 32-channel signal processing in a single Xilinx Artix-7 Field-Programmable Gate Array (FPGA). The logic is designed to support four online modes which are regular data processing mode, flood map construction mode, energy spectrum construction mode, and raw data mode. Several functions are integrated, including two-dimensional (2D) raw position calculation, crystal locating, events filtering, and synchronization detection. Furthermore, a series of online corrections is also integrated, such as photon peak correction to 511 keV and time measurement result correction with crystal granularity. A Gigabit Ethernet Interface is utilized for data transfer, Look-Up Tables (LUTs) configuration, and command issuing. The pipeline logic works at 125 MHz with a signal processing capability beyond the required data rate of 1,000,000 events/s/channel. A series of initial tests are conducted. The results indicate that the logic design meets the application requirement.

  • A Design of FPGA Based Small Animal PET Real Time Digital Signal Processing and Correction Logic
    arXiv: Signal Processing, 2018
    Co-Authors: Lei Zhao, Kairen Chen, Peipei Deng, Liu Shubin
    Abstract:

    Small animal Positron Emission Tomography (PET) is dedicated to small animal imaging. Animals used in experiments, such as rats and monkeys, are often much smaller than human bodies, which requires higher position and energy precision of the PET imaging system. Besides, Flexibility, high efficiency are also the major demands of a practical PET system. These requires a high-quality analog front-end and a digital signal processing logic with high efficiency and compatibility of multiple data processing modes. The digital signal processing logic of the small animal PET system presented in this paper implements 32-channel signal processing in a single Xilinx Artix-7 family of Field-Programmable Gate Array (FPGA). The logic is designed to support three online modes which are regular package mode, flood map and energy spectrum histogram. Several functions are integrated, including two-dimensional (2D) raw position calculation, crystal identification, events filtering, etc. Besides, a series of online corrections are also integrated, such as photon peak correction to 511 keV and timing offset correction with crystal granularity. A Gigabit Ethernet Interface is utilized for data transfer, Look-Up Tables (LUTs) configuration and commands issuing. The pipe-line logic processes the signals at 125 MHz with a rate of 1,000,000 events/s. A series of initial tests are conducted. The results indicate that the digital processing logic achieves the expectations.

Lahatra Rakotondrainibe - One of the best experts on this subject based on the ideXlab platform.

  • 60 GHz High Data Rate Wireless Communication System
    VTC 2009, 2009
    Co-Authors: Lahatra Rakotondrainibe, Yvan Kokar, Gheorghe Zaharia, Ghaïs El Zein
    Abstract:

    This paper presents the design and the realization of a 60 GHz wireless Gigabit Ethernet communication system. A differential encoded binary phase shift keying modulation (DBPSK) and differential demodulation schemes are adopted for the IF blocks. The Gigabit Ethernet Interface allows a high speed transfer of multimedia files via a 60 GHz wireless link. First measurement results are shown for 875 Mbps data rate.

  • VTC Spring - 60 GHz High Data Rate Wireless Communication System
    VTC Spring 2009 - IEEE 69th Vehicular Technology Conference, 2009
    Co-Authors: Lahatra Rakotondrainibe, Yvan Kokar, Gheorghe Zaharia, Ghaïs El Zein
    Abstract:

    This paper presents the design and the realization of a 60 GHz wireless Gigabit Ethernet communication system. A differential encoded binary phase shift keying modulation (DBPSK) and differential demodulation schemes are adopted for the IF blocks. The Gigabit Ethernet Interface allows a high speed transfer of multimedia files via a 60 GHz wireless link. First measurement results are shown for 875 Mbps data rate.

Kairen Chen - One of the best experts on this subject based on the ideXlab platform.

  • Real-Time FPGA-based Digital Signal Processing and Correction for a Small Animal PET
    IEEE Transactions on Nuclear Science, 2019
    Co-Authors: Lei Zhao, Kairen Chen, Peipei Deng, Shubin Liu
    Abstract:

    Small animal Positron Emission Tomography (PET) is dedicated to small animal imaging, which requires high position and energy precision, as well as good flexibility and efficiency of the electronics. This paper presents the design of a digital signal processing logic for a marmoset brain PET system based on LYSO crystal arrays, SiPMs, and the resistive network readout method. We implement 32-channel signal processing in a single Xilinx Artix-7 Field-Programmable Gate Array (FPGA). The logic is designed to support four online modes which are regular data processing mode, flood map construction mode, energy spectrum construction mode, and raw data mode. Several functions are integrated, including two-dimensional (2D) raw position calculation, crystal locating, events filtering, and synchronization detection. Furthermore, a series of online corrections is also integrated, such as photon peak correction to 511 keV and time measurement result correction with crystal granularity. A Gigabit Ethernet Interface is utilized for data transfer, Look-Up Tables (LUTs) configuration, and command issuing. The pipeline logic works at 125 MHz with a signal processing capability beyond the required data rate of 1,000,000 events/s/channel. A series of initial tests are conducted. The results indicate that the logic design meets the application requirement.

  • A Design of FPGA Based Small Animal PET Real Time Digital Signal Processing and Correction Logic
    arXiv: Signal Processing, 2018
    Co-Authors: Lei Zhao, Kairen Chen, Peipei Deng, Liu Shubin
    Abstract:

    Small animal Positron Emission Tomography (PET) is dedicated to small animal imaging. Animals used in experiments, such as rats and monkeys, are often much smaller than human bodies, which requires higher position and energy precision of the PET imaging system. Besides, Flexibility, high efficiency are also the major demands of a practical PET system. These requires a high-quality analog front-end and a digital signal processing logic with high efficiency and compatibility of multiple data processing modes. The digital signal processing logic of the small animal PET system presented in this paper implements 32-channel signal processing in a single Xilinx Artix-7 family of Field-Programmable Gate Array (FPGA). The logic is designed to support three online modes which are regular package mode, flood map and energy spectrum histogram. Several functions are integrated, including two-dimensional (2D) raw position calculation, crystal identification, events filtering, etc. Besides, a series of online corrections are also integrated, such as photon peak correction to 511 keV and timing offset correction with crystal granularity. A Gigabit Ethernet Interface is utilized for data transfer, Look-Up Tables (LUTs) configuration and commands issuing. The pipe-line logic processes the signals at 125 MHz with a rate of 1,000,000 events/s. A series of initial tests are conducted. The results indicate that the digital processing logic achieves the expectations.