The Experts below are selected from a list of 32046 Experts worldwide ranked by ideXlab platform
Greg Stitt - One of the best experts on this subject based on the ideXlab platform.
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offloading cache configuration prediction to an fpga for Hardware speedup and Overhead reduction work in progress
International Conference on Hardware Software Codesign and System Synthesis, 2019Co-Authors: Ruben Vazquez, Ann Gordonross, Greg StittAbstract:In this paper, we present our cache configuration prediction methodology offloaded to an FPGA for improved performance and Hardware Overhead reduction, while maintaining cache configuration predictions within 5% of the optimal energy cache configuration for application phases for the instruction and data caches.
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work in progress offloading cache configuration prediction to an fpga for Hardware speedup and Overhead reduction
International Conference on Hardware Software Codesign and System Synthesis, 2019Co-Authors: Ruben Vazquez, Ann Gordonross, Greg StittAbstract:In this paper, we present our cache configuration prediction methodology offloaded to an FPGA for improved performance and Hardware Overhead reduction, while maintaining cache configuration predictions within 5% of the optimal energy cache configuration for application phases for the instruction and data caches.
Ruben Vazquez - One of the best experts on this subject based on the ideXlab platform.
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offloading cache configuration prediction to an fpga for Hardware speedup and Overhead reduction work in progress
International Conference on Hardware Software Codesign and System Synthesis, 2019Co-Authors: Ruben Vazquez, Ann Gordonross, Greg StittAbstract:In this paper, we present our cache configuration prediction methodology offloaded to an FPGA for improved performance and Hardware Overhead reduction, while maintaining cache configuration predictions within 5% of the optimal energy cache configuration for application phases for the instruction and data caches.
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work in progress offloading cache configuration prediction to an fpga for Hardware speedup and Overhead reduction
International Conference on Hardware Software Codesign and System Synthesis, 2019Co-Authors: Ruben Vazquez, Ann Gordonross, Greg StittAbstract:In this paper, we present our cache configuration prediction methodology offloaded to an FPGA for improved performance and Hardware Overhead reduction, while maintaining cache configuration predictions within 5% of the optimal energy cache configuration for application phases for the instruction and data caches.
Ramesh Karri - One of the best experts on this subject based on the ideXlab platform.
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tao techniques for algorithm level obfuscation during high level synthesis
Design Automation Conference, 2018Co-Authors: Christian Pilato, Ramesh Karri, Francesco Regazzoni, Siddharth GargAbstract:Intellectual Property (IP) theft costs semiconductor design companies billions of dollars every year. Unauthorized IP copies start from reverse engineering the given chip. Existing techniques to protect against IP theft aim to hide the IC's functionality, but focus on manipulating the HDL descriptions. We propose TAO as a comprehensive solution based on high-level synthesis to raise the abstraction level and apply algorithmic obfuscation automatically. TAO includes several transformations that make the component hard to reverse engineer during chip fabrication, while a key is later inserted to unlock the functionality. Finally, this is a promising approach to obfuscate large-scale designs despite the Hardware Overhead needed to implement the obfuscation.
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design and analysis of ring oscillator based design for trust technique
VLSI Test Symposium, 2011Co-Authors: Jeyavijayan Rajendran, Vinayaka Jyothi, Ozgur Sinanoglu, Ramesh KarriAbstract:Due to the increasing opportunities for malicious inclusions in Hardware, Design-for-Trust (DFTr) is emerging as an important IC design methodology. In order to incorporate the DFTr techniques into the IC development cycle, they have to be practical in terms of their Trojan detection capabilities, Hardware Overhead, and test cost. We propose a non-invasive DFTr technique, which can detect Trojans in the presence of process variations and measurement errors. This technique can detect Trojans that are inserted in all or a subset of the ICs. It is applicable to both ASICs and FPGA implementations. Circuit paths in a design are reconfigured into ring oscillators1 (ROs) by adding a small amount of logic. Trojans are detected by observing the changes in the frequency of the ROs. An algorithm is provided to secure all the gates, while reducing the Hardware Overhead. We analyzed the coverage, area and test time Overhead of the proposed DFTr technique. To demonstrate its effectiveness in the real world, the proposed technique had been validated by a red-team blue-team approach.
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Fault secure datapath synthesis using hybrid time and Hardware redundancy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2004Co-Authors: Kaijie Wu, Ramesh KarriAbstract:A fault-secure datapath either generates a correct result or signals an error. This paper presents a register transfer level concurrent error detection (CED) technique that uses hybrid time and Hardware redundancy to optimize the time and area Overhead associated with fault security. The proposed technique combines the idle computation cycles in a datapath with selective breaking of data dependences of the normal computation. Designers can tradeoff time and Hardware Overhead by varying these design parameters. We present an algorithm to synthesize fault secure designs and validate it using Synopsys' behavioral compiler.
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register transfer level approach to hybrid time and Hardware redundancy based fault secure datapath synthesis
International Test Conference, 2003Co-Authors: Ramesh KarriAbstract:A fault-secure datapath either generates a correct result or signals an error. This paper presents a register transfer level Concurrent Error Detection (CEO) technique that uses hybrid time and Hardware redundancy to optimize the time and area Overhead associated with fault security. The proposed technique combines the idle computation cycles in a datapath with selective breaking of data dependences of the normal computation. Designers can trade-off time and Hardware Overhead by varying these design parameters. We present an algorithm to synthesize fault secure designs and validate it using Synopsys Behavioral Compiler.
Ann Gordonross - One of the best experts on this subject based on the ideXlab platform.
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offloading cache configuration prediction to an fpga for Hardware speedup and Overhead reduction work in progress
International Conference on Hardware Software Codesign and System Synthesis, 2019Co-Authors: Ruben Vazquez, Ann Gordonross, Greg StittAbstract:In this paper, we present our cache configuration prediction methodology offloaded to an FPGA for improved performance and Hardware Overhead reduction, while maintaining cache configuration predictions within 5% of the optimal energy cache configuration for application phases for the instruction and data caches.
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work in progress offloading cache configuration prediction to an fpga for Hardware speedup and Overhead reduction
International Conference on Hardware Software Codesign and System Synthesis, 2019Co-Authors: Ruben Vazquez, Ann Gordonross, Greg StittAbstract:In this paper, we present our cache configuration prediction methodology offloaded to an FPGA for improved performance and Hardware Overhead reduction, while maintaining cache configuration predictions within 5% of the optimal energy cache configuration for application phases for the instruction and data caches.
Sungho Kang - One of the best experts on this subject based on the ideXlab platform.
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a low cost concurrent tsv test architecture with lossless test output compression scheme
PLOS ONE, 2019Co-Authors: Youngwoo Lee, Keewon Cho, Hyunchan Lim, Sungyoul Seo, Sungho KangAbstract:As the traditional IC design migrates to three-dimensional integrated circuits (3D-ICs) design, new challenges need to be considered carefully to solve its reliability and yield issues. 3D-ICs using through-silicon-vias (TSVs) can have latent defects such as resistive open and bridge defects, which are caused by the thermal stress during the fabrication process. These latent defects lead to the deterioration of the electrical performance of TSVs caused by an undesired increase in the resistance-capacitance (RC) delay. For this reason, various post-bond test methodologies have been studied to improve the reliability of 3D-ICs. Cost reduction in these TSV test architectures is also currently being studied by decreasing various factors such as Hardware Overhead, test time, and the peak current consumption. Usually, a single test-clock-period is required to determine whether the test result contains the defective TSV. When the test result of any TSVs fails, we use another single test-clock-period to classify its defect type. In this paper, we propose a new TSV test architecture to transfer the combined test output of the test result and the specific defect type to the pad during the single test-clock-period. Our proposed test architecture also provides a reliable block-based concurrent testing to optimize the test time by dividing the die into concurrent blocks. The experimental results showed that our proposed test architecture could reduce the test time and the Hardware Overhead substantially by ensuring that the reasonable peak power consumption for mass production was reasonable without the test quality being adversely affected.
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Hardware efficient built in redundancy analysis for memory with various spares
IEEE Transactions on Very Large Scale Integration Systems, 2017Co-Authors: Joo Young Kim, Woosung Lee, Keewon Cho, Sungho KangAbstract:Memory capacity continues to increase, and many semiconductor manufacturing companies are trying to stack memory dice for larger memory capacities. Therefore, built-in redundancy analysis (BIRA) is of utmost importance because the probability of fault occurrence increases with a larger memory capacity. A traditional spare structure that consists of simple rows and columns is somewhat inadequate for multiple memory blocks BIRA because the Hardware Overhead and spare allocation efficiency are degraded. The proposed BIRA uses various types of spares and can achieve a higher yield than a simple row and column spare structure. Herein, we propose a BIRA that can achieve an optimal repair rate using various spare types. The proposed analyzer can exhaustively search not only row and column spare types but also global and local spare types. In addition, this paper proposes a fault-storing content-addressable memory (CAM) structure. The proposed CAM is small and collects faults efficiently. The experimental results show a high repair rate with a small Hardware Overhead and a short analysis time.
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near optimal repair rate built in redundancy analysis with very small Hardware Overhead
International Symposium on Quality Electronic Design, 2015Co-Authors: Woosung Lee, Keewon Cho, Joo Young Kim, Sungho KangAbstract:As the memory density and capacity grows, it is more likely that the number of defects increases. For this reason, in order to improve memory yield, repair analysis is widely used. Built-in redundancy analysis (BIRA) is regarded as one of the solutions to improve memory yield. However, the previous BIRA approaches require large Hardware Overhead to achieve an optimal repair rate. This is the main obstacle to use BIRA practically. Therefore, a new BIRA is proposed to reduce the Hardware Overhead significantly using spare allocation probability according to the number of faults on a sparse faulty line. The experimental results show that the Hardware Overhead of the proposed approach can be considerably reduced with slight loss of repair rate. Therefore, it can be used as a practical solution for BIRA.
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a pattern group partitioning for parallel string matching using a pattern grouping metric
IEEE Communications Letters, 2010Co-Authors: Sungho KangAbstract:Considering the increasing number of target patterns for the intrusion detection systems (IDS), memory requirements should be minimized for reducing Hardware Overhead. This paper proposes an algorithm that partitions a set of target patterns into multiple subgroups for homogeneous string matchers. Using a pattern grouping metric, the proposed pattern partitioning makes the average length of the mapped target patterns onto a string matcher approximately equal to the average length of total target patterns. Therefore, the variety of target pattern lengths can be mitigated because the number of mapped target patterns onto each string matcher is balanced.
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an efficient bist architecture for embedded rams
ICEIC : International Conference on Electronics Informations and Communications, 2008Co-Authors: Youngkyu Park, Jaeseok Park, Sungho KangAbstract:In this paper, a new BIST(Built-In Self-Test) structure for efficient test of embedded RAMs is proposed. In proposed embedded memory BIST(EMBIST) architecture, various algorithms are allowed to be executed, and just one controller can test more than one embedded memories. And, the proposed EMBIST has efficient structure that requires smaller Hardware Overhead. The experimental result demonstrates the effectiveness of proposed EMBIST architecture.
