Hardware Register

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The Experts below are selected from a list of 81 Experts worldwide ranked by ideXlab platform

Glenn Holloway - One of the best experts on this subject based on the ideXlab platform.

  • PLDI - A generalized algorithm for graph-coloring Register allocation
    Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation - PLDI '04, 2004
    Co-Authors: Michael D. Smith, Norman F. Ramsey, Glenn Holloway
    Abstract:

    Graph-coloring Register allocation is an elegant and extremely popular optimization for modern machines. But as currently formulated, it does not handle two characteristics commonly found in commercial architectures. First, a single Register name may appear in multiple Register classes, where a class is a set of Register names that are interchangeable in a particular role. Second, multiple Register names may be aliases for a single Hardware Register. We present a generalization of graph-coloring Register allocation that handles these problematic characteristics while preserving the elegance and practicality of traditional graph coloring. Our generalization adapts easily to a new target machine, requiring only the sets of names in the Register classes and a map of the Register aliases. It also drops easily into a well-known graph-coloring allocator, is efficient at compile time, and produces high-quality code.

  • a generalized algorithm for graph coloring Register allocation
    Programming Language Design and Implementation, 2004
    Co-Authors: Michael D. Smith, Norman F. Ramsey, Glenn Holloway
    Abstract:

    Graph-coloring Register allocation is an elegant and extremely popular optimization for modern machines. But as currently formulated, it does not handle two characteristics commonly found in commercial architectures. First, a single Register name may appear in multiple Register classes, where a class is a set of Register names that are interchangeable in a particular role. Second, multiple Register names may be aliases for a single Hardware Register. We present a generalization of graph-coloring Register allocation that handles these problematic characteristics while preserving the elegance and practicality of traditional graph coloring. Our generalization adapts easily to a new target machine, requiring only the sets of names in the Register classes and a map of the Register aliases. It also drops easily into a well-known graph-coloring allocator, is efficient at compile time, and produces high-quality code.

Michael D. Smith - One of the best experts on this subject based on the ideXlab platform.

  • PLDI - A generalized algorithm for graph-coloring Register allocation
    Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation - PLDI '04, 2004
    Co-Authors: Michael D. Smith, Norman F. Ramsey, Glenn Holloway
    Abstract:

    Graph-coloring Register allocation is an elegant and extremely popular optimization for modern machines. But as currently formulated, it does not handle two characteristics commonly found in commercial architectures. First, a single Register name may appear in multiple Register classes, where a class is a set of Register names that are interchangeable in a particular role. Second, multiple Register names may be aliases for a single Hardware Register. We present a generalization of graph-coloring Register allocation that handles these problematic characteristics while preserving the elegance and practicality of traditional graph coloring. Our generalization adapts easily to a new target machine, requiring only the sets of names in the Register classes and a map of the Register aliases. It also drops easily into a well-known graph-coloring allocator, is efficient at compile time, and produces high-quality code.

  • a generalized algorithm for graph coloring Register allocation
    Programming Language Design and Implementation, 2004
    Co-Authors: Michael D. Smith, Norman F. Ramsey, Glenn Holloway
    Abstract:

    Graph-coloring Register allocation is an elegant and extremely popular optimization for modern machines. But as currently formulated, it does not handle two characteristics commonly found in commercial architectures. First, a single Register name may appear in multiple Register classes, where a class is a set of Register names that are interchangeable in a particular role. Second, multiple Register names may be aliases for a single Hardware Register. We present a generalization of graph-coloring Register allocation that handles these problematic characteristics while preserving the elegance and practicality of traditional graph coloring. Our generalization adapts easily to a new target machine, requiring only the sets of names in the Register classes and a map of the Register aliases. It also drops easily into a well-known graph-coloring allocator, is efficient at compile time, and produces high-quality code.

Sumedh W. Sathaye - One of the best experts on this subject based on the ideXlab platform.

  • Efficient Instruction Scheduling with Precise Exceptions
    2003
    Co-Authors: Erik R. Altman, Kemal Ebcioglu, Michael K. Gschwind, Sumedh W. Sathaye
    Abstract:

    We describe the SPACE algorithm for translating from one architecture such as PowerPC into operations for another architecture such as VLIW, while also supporting scheduling, Register al- location, and other optimizations. Our SPACE algorithm supports precise exceptions, but in an improvement over our previous work, eliminates the need for most Hardware Register commit op- erations, which are used to place values in their original program location in the original program sequence. The elimination of commit operations frees issue slots for other computation, a feature that is especially important for narrower machines. The SPACE algorithm is efficient, running in O(N) time in the number N of operations in the worst case, but in practice is closer to a two-pass O(N) algorithm. The fact that our approach provides precise exceptions with low overhead is useful to program- ming language designers as well — exception models in which an exception can occur at almost any instruction are not prohibitively expensive.

  • IBM Research Report Efficient Instruction Scheduling with Precise Exceptions
    1999
    Co-Authors: Erik R. Altman, Kemal Ebcioglu, Michael K. Gschwind, Sumedh W. Sathaye
    Abstract:

    AbstractWe describe the SPACE algorithm for translating from one architecture such as PowerPC intooperations for another architecture such as VLIW, while also supporting scheduling, Register al-location, and other optimizations. Our SPACE algorithm supports precise exceptions, but in animprovement over our previous work, eliminates the need for most Hardware Register commit op-erations, which are used to place values in their original program location in the original programsequence. The elimination of commit operations frees issue slots for other computation, a featurethat is especially important for narrower machines. The SPACE algorithm is efficient, running in O(N2) time in the number of operations in the worst case, but in practice is closer to a two-pass O(N) algorithm.The fact that our approach provides precise exceptions with low overhead is useful to program-ming language designers as well — exception models in which an exception can occur at almostany instruction are not prohibitively expensive.

G. Welch - One of the best experts on this subject based on the ideXlab platform.

  • ICCV - Ensuring color consistency across multiple cameras
    Tenth IEEE International Conference on Computer Vision (ICCV'05) Volume 1, 2005
    Co-Authors: Adelina Ilie, G. Welch
    Abstract:

    Most multi-camera vision applications assume a single common color response for all cameras. However different cameras - even of the same type - can exhibit radically different color responses, and the differences can cause significant errors in scene interpretation. To address this problem we have developed a robust system aimed at inter-camera color consistency. Our method consists of two phases: an iterative closed-loop calibration phase that searches for the per-camera Hardware Register settings that best balance linearity and dynamic range, followed by a refinement phase that computes the per-camera parametric values for an additional software-based color mapping

Norman F. Ramsey - One of the best experts on this subject based on the ideXlab platform.

  • PLDI - A generalized algorithm for graph-coloring Register allocation
    Proceedings of the ACM SIGPLAN 2004 conference on Programming language design and implementation - PLDI '04, 2004
    Co-Authors: Michael D. Smith, Norman F. Ramsey, Glenn Holloway
    Abstract:

    Graph-coloring Register allocation is an elegant and extremely popular optimization for modern machines. But as currently formulated, it does not handle two characteristics commonly found in commercial architectures. First, a single Register name may appear in multiple Register classes, where a class is a set of Register names that are interchangeable in a particular role. Second, multiple Register names may be aliases for a single Hardware Register. We present a generalization of graph-coloring Register allocation that handles these problematic characteristics while preserving the elegance and practicality of traditional graph coloring. Our generalization adapts easily to a new target machine, requiring only the sets of names in the Register classes and a map of the Register aliases. It also drops easily into a well-known graph-coloring allocator, is efficient at compile time, and produces high-quality code.

  • a generalized algorithm for graph coloring Register allocation
    Programming Language Design and Implementation, 2004
    Co-Authors: Michael D. Smith, Norman F. Ramsey, Glenn Holloway
    Abstract:

    Graph-coloring Register allocation is an elegant and extremely popular optimization for modern machines. But as currently formulated, it does not handle two characteristics commonly found in commercial architectures. First, a single Register name may appear in multiple Register classes, where a class is a set of Register names that are interchangeable in a particular role. Second, multiple Register names may be aliases for a single Hardware Register. We present a generalization of graph-coloring Register allocation that handles these problematic characteristics while preserving the elegance and practicality of traditional graph coloring. Our generalization adapts easily to a new target machine, requiring only the sets of names in the Register classes and a map of the Register aliases. It also drops easily into a well-known graph-coloring allocator, is efficient at compile time, and produces high-quality code.